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Packaging and testing6 min read

How are chips tested, and how is wafer sort (CP) different from final test (FT)?

Chips are usually tested twice after they are made. The first time, they are still on the uncut wafer: this is called wafer test, wafer sort, probe test or CP. The second time comes after each chip has been packaged: this is final test, often called FT. Wafer sort weeds out bad chips so no money is spent packaging them; final test checks that the packaged parts are still good before they ship.

Why test every single chip?

A wafer goes through hundreds of steps in the fab, and any of them can ruin a few chips, so every wafer has some bad ones. What does "yield" mean in chip news? explains why it never reaches 100%.

The trouble is that you can't see which ones are bad. A chip often holds tens of millions to tens of billions of tiny switches, and looking through a microscope alone won't show you the one that doesn't work. The only way to find out is to power the chip up, give it work to do and check whether the answers are right.

So chip testing isn't a spot check. Every chip takes the exam, the way every student in a class sits the test, not just a few picked at random.

How does wafer sort (CP) work?

When the wafers are finished, they often go to a test-and-assembly house or a dedicated test house. The equipment has two halves: a test machine sends power and signals and reads back the results, and a probe station holds the wafer flat, lines it up and steps it from chip to chip.

Between the two sits a probe card: a board with many very fine needles, placed exactly where the chip's pads are. Pads are small patches of metal on the chip's surface, the points where it connects to the outside for power and signals. Once the needles touch down, the test machine can "talk" to the chip. When one chip is done, the probe station steps the wafer to the next; many probe cards touch several chips at once to save time.

After many touchdowns, the needles wear and pick up debris. A dirty needle makes poor contact, and then good chips measure as bad, so the needles are cleaned regularly.

Why test before the wafer is cut?

To save money. Packaging takes materials, machine time and labor; package a bad chip and all of that is wasted.

After the test, each chip is sorted by its result: good chips in one group, bad ones in a group for each way of failing. These groups are called bins. The results are drawn by position as a wafer map. Bad chips used to get a dot of ink; today the map is usually just kept as a file, and after the wafer is cut, the die attach machine follows it and picks up only the good chips for packaging.

The wafer map is also a clue. If the bad chips form a ring or a neat grid, that often points to the step that went wrong.

Before wafers leave the fab, they also go through WAT, which is easy to confuse with wafer sort. WAT measures small structures between the chips that are there only for measuring, to see whether the lot was made right; wafer sort tests every chip itself.

Why test again after packaging?

Because packaging can damage a chip too. The wafer is cut apart, each chip is glued onto a board, fine wires are bonded one by one, and the whole thing is sealed in plastic (each step is explained in What is chip packaging?). A corner can chip off during cutting, a wire may not hold, and the plastic flowing in can push wires sideways until they touch. Some characteristics also change once a chip is packaged.

And some checks only work after packaging. The simplest example: the pins on the case, the solder balls underneath and the wires inside don't exist yet on the wafer. Some products put the chip together with small parts in one module, and the module can only be tested as a whole once it is built.

Final test uses a machine called a handler. It picks up packaged chips and places them in a test socket that connects to their pins, then sorts them into different trays by result. To save time, it often loads several at once and tests them together.

On the wafer, not every item can be tested as fully as after packaging, either. Which checks run at wafer sort and which wait for final test is a trade-off between test time, cost and yield.

What is actually being tested?

There are many items, but in plain terms they fall into a few groups:

  • Is it connected? Is every pad and every pin connected, and are any two touching where they shouldn't be?
  • Does it work? Feed in a set of inputs from the design and check that the outputs match the right answers.
  • Is it fast enough? Does it still get the right answers at the specified speed? Some products are also graded by how fast they can run: the fastest go in one bin, slower ones in another.
  • How much does it leak in standby? Even when a chip is "off", a little current leaks through. Too much, and a battery-powered device like a phone or a hearing aid won't last.
  • Does it work hot and cold? A chip behaves differently as the temperature changes. Some products are tested once hot and once cold to make sure they stay within spec.

These questions are written into a test program. It is the exam paper: what each question checks and what score counts as a pass. Where to set the pass mark, the upper and lower limits, is a trade-off: too tight and good chips are thrown out; too loose and bad ones reach the customer.

CP vs FT at a glance

Wafer sort (CP)Final test (FT)
WhenAfter the wafer is made, before it is cutAfter packaging, before shipping
What is testedBare chips still on the waferPackaged chips or modules
How it connectsProbe card needles touch the padsA test socket touches the pins or solder balls
What forRemove bad chips before paying to package themCheck that packaged parts are still good
AfterwardsA wafer map; only good chips get packagedSorted into trays by bin; only good ones ship

Testing asks "is it good now?"; "will it still work after a while?" is a separate subject called reliability, for example running chips powered at high temperature for a while to count the early-life failures, the ones that break soon after they start being used. It will get its own article.

In fab24hr

In fab24hr's main story, The life of a chip, "Glowmere", a fictional hearing-aid chip, is tested more than once. In chapter 3, on the R&D line, the first wafers come back from wafer sort and you work out what the odd shapes on three wafer maps each point to. In chapter 10, at the test-and-assembly house, you are the test engineer: first you find which kind of failure fills the most bins, then you decide where to draw the standby current limit and write it into the test program.

In "A day in the fab", tap "Switch roles", pick "Test-and-assembly house" and choose the test engineer; all four shifts take place in the wafer test area. Late at night, one set of needles on a probe card is dirty, and the same position keeps measuring good chips as bad. The morning is the chapter 10 shift. In the afternoon, a few chips are within the limit but stand well above their neighbors, and you decide whether to screen them out. In the evening, two test machines disagree, and you check them with a wafer whose answers are already known. Final test is in another part of the same test-and-assembly house; the customer liaison's afternoon shift goes there to find the 12 modules that never reached a bin after the handler jammed.

The test-and-assembly house, the chip, the people and the numbers in the game are fictional; what testing does and why chips are tested twice come from public, general sources. For other jargon, see Chip fab jargon in plain English.

Where you'll meet it in the gameIn chapter 3 of the main story, The life of a chip, the R&D line's first wafers come back from wafer sort and you read the wafer maps; in chapter 10, as the test engineer at a test-and-assembly house, you look at the bins and write the standby current limit into the test program. In "A day in the fab", all four of the test engineer's shifts take place in the wafer test area.

In fab24hr, the test engineer spends the day between the probe stations and the bin screen: a dirty probe card, two test machines that disagree, where to draw a limit. Those calls are yours.

Play as the test engineer and look after every chip's test

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