Semiconductors 101: a free course following the life of a chip
For anyone who wants to learn about semiconductors from zero
A free syllabus that follows the life of a chip: from what the semiconductor industry does, through how a fab builds a chip layer by layer and how it knows it was done right, to the people who work there and the future. Each unit has one or more plain-language articles, a chapter or shift of the game fab24hr, and discussion questions with no single right answer; most units on the fab and on packaging and testing also have a 3D machine you can take apart. No install, no sign-in; you can read and play it all on a phone.
Part 1: What semiconductors do
- 1What semiconductors and chips are
- 2Transistors: tens of billions of switches
- 3The supply chain: who does what, and how they work together
- 6Wafers and cleanrooms
- 7How chips are made: the big picture
- 8Wet clean: washing wafers between steps
- 9Furnace: oxidation and annealing in the heat
- 10Thin film: building up layer by layer
- 11Lithography: printing the pattern
- 12Etch: cutting the pattern in
- 13Doping: ion implant and annealing
- 14Wiring and polishing: CMP and layer upon layer of metal
- 15Process integration: putting hundreds of steps in order
- 16A factory that never stops
Part 4: How do you know it was done right?
- 17Metrology and inspection: what to measure, and how many wafers
- 18Control charts and daily monitoring
- 19Yield and wafer maps
- 20When something goes wrong: from the alarm to "never again"
Part 5: After the wafer is finished
- 23The people in a fab: roles, shifts and careers
- 24From R&D to production: who goes first, and how the handoff works
- 25How small can transistors get? The story of "nanometers"
- 26Advanced packaging and new materials: more than shrinking
- 27Making sense of chip news
Part 1: What semiconductors do
What a chip is, what the switches inside it, up to tens of billions, do, and what each part of the industry, from upstream to downstream, does and how they work together.
Unit 1What semiconductors and chips are
"Semiconductor" often means both a material and a whole industry. Start by sorting out the words people mix up most: semiconductor, wafer, chip and integrated circuit.
Goals
- Explain how a semiconductor differs from a conductor and an insulator, and why being able to control whether it conducts matters so much.
- Tell a wafer, a chip and an integrated circuit apart, and name the kinds of companies that share the work in "the chip industry".
- Outline the three stages a chip goes through: design, manufacturing in a fab, and assembly and test.
- ReadSemiconductors 101: what is a semiconductor, and what does a chip fab do?What is a semiconductor, and why is it called "semi"?What is a chip, and how is it different from a wafer, an IC or a semiconductor?
- PlayTap "Clock in" to start: choose "The life of a chip" to follow one chip all the way, or "A day in the fab" to work one shift as someone in the fab
Think
- Which things around you contain chips? If the world had half as many chips tomorrow, where would your day get stuck first?
- A chip is finished by several kinds of companies sharing the work, not by one company from start to finish. What does that division of labor gain, and what risks does it bring?
Unit 2Transistors: tens of billions of switches
A chip can compute and remember because it holds a great many tiny switches controlled by electricity; a phone chip has more than ten billion. This unit goes from a single switch to processors and memory.
Goals
- Explain what a transistor does using the idea of a switch, why it is normally off, and that a 0 or a 1 is really the voltage on a wire.
- Explain why two kinds of switch are paired (CMOS), how switches in series and in parallel become logic gates, and how gates make a circuit that adds.
- Describe what making transistors smaller gains, and why a chip uses power even when it is doing nothing.
- ReadWhat is a transistor, and why does a phone chip hold billions of them?What is CMOS, and why do chip switches come in pairs?What are logic gates, and how do switches become a chip that computes?
- FurtherHow is memory different from a processor, and DRAM from flash?Why do chips use power? Leakage and standby current, explained
- PlayStart at chapter 10, "Standby Current": a chip that does nothing yet draws too much power
Think
- A phone left alone still slowly loses charge. Where does the energy go? Try to explain it with what you read in this unit.
- One kind of memory forgets when the power is cut; another remembers. Why does a phone need both? Can you think of a similar division of labor in everyday life?
Unit 3The supply chain: who does what, and how they work together
On its way from materials, design, masks and the wafer fab through assembly and test to the inside of a phone, a chip often passes through several companies. First see what each stop does and why it is often a different company, then follow one order from choosing a process to the wafers arriving at the test-and-assembly house.
Goals
- Say what each stop on the supply chain does and why it is often a different company, and tell which way of slicing the chain a news story means by upstream, midstream and downstream.
- Tell fabless design companies, foundries, IDMs and test-and-assembly houses apart, say why the work is split this way, and why one broken link slows the whole chain.
- Walk through each step a design company takes, from choosing a process, tape-out, masks and wafer start to the test-and-assembly house, and say why a new product often shares a ride first and starts with engineering lots.
- ReadWhat does each part of the semiconductor supply chain do?The news says "fabless", "foundry" and "IDM". What's the difference?The news says "foundry". What is it, and how does making chips for other companies work as a business?How does a chip design company work with a foundry, from order to delivery?
- FurtherWhy are chips so expensive?
- PlayStart at chapter 4, "Two Weeks Early": the reliability test still has three weeks to run, the customer wants a risk start, and you give your recommendation
Think
- A foundry often makes chips for several competing companies at once. If you ran a small design company, what would you want to ask before handing over your most valuable asset, the design?
- For a first chip, you can share a ride on a multi-project wafer (MPW), or make your own full mask set right away. If it were your call, what would you look at, and what does each choice cost you?
Part 2: Before a chip is born
How a chip goes from a need to a design that is sent out to be made into photomasks, before it ever reaches the fab.
Unit 4Needs, specs and IC design
Before a chip goes into a fab, it is designed in full on computers and checked many times: a large chip has more than ten billion transistors, far too many to draw or check by hand, so every step relies on design software, and some blocks are even bought. Every step from "what should it do" to handing over the design is there to avoid finding a mistake after tape-out.
Goals
- Outline the order of digital chip design, from the spec, writing the behavior, verification, synthesis and place and route to sign-off and tape-out, and which kind of design software (EDA) each step uses.
- Explain how verification is done, setting tests from the spec, checking coverage and proving things with math, and why a mistake found after tape-out is so costly.
- Know which blocks in a chip are often bought as semiconductor IP, how soft and hard IP differ, and how a fab's rules reach the design through the PDK.
- ReadHow are chips designed, and what does IC design involve?What is semiconductor IP, and why do chips contain circuits someone else designed?What is EDA, and what does chip design software do at each step?What is chip verification, and how do you know a design is right before tape-out?
- FurtherWhat is an SoC, the "system on a chip" in your phone?Analog vs digital chips: what's the difference?VLSI design vs working in a fab: what's the difference?
- PlayStart at chapter 1, "How to Split 12": make the corners the design was simulated at for real, and see whether the design holds up
Think
- A small hearing-aid company is designing its own chip for the first time. The analog circuit that turns the microphone's sound into numbers and the clock circuit that sets the beat for the whole chip could be drawn in-house or bought as ready-made IP. How would you decide which to do yourself and which to buy? What would you ask the seller before buying?
- Verification takes a lot of people and time, but doing less of it risks finding a mistake after tape-out. If the schedule were tight, how would you decide that "this is enough checking"?
Unit 5Masks and tape-out: how a design becomes a mask set
Handing a checked design to the fab is called tape-out, and changing it after that means new masks. The design can't be printed as it is either: it first has to be corrected and made into a set of photomasks. A mask is the "negative" for exposure, and one printable spot or one small error on it prints in every field of every wafer, so it has to be drawn extremely accurately and checked extremely closely.
Goals
- Say what is checked one last time before tape-out, what is handed over, and why changing the design after tape-out is costly and slow.
- Say how a mask prints its pattern onto the wafer, why one chip design needs dozens of masks, and why the pattern is deliberately changed first with OPC, with computers working out how much.
- Know how a mask is written, inspected and repaired, why a set costs so much, and why it is checked again once it reaches the fab.
- ReadWhat is tape-out, and what happens after a chip design is handed off?What is a photomask? How is it made, and why does a set cost so much?What is OPC, and why doesn't the photomask look like the chip?
- FurtherWhat does a mask engineer do in a chip fab?
- PlayPlay a shift as the mask engineer: when a mask has haze, a new spot or a scratch, you decide whether it can still go on the scanner
Think
- The finer the OPC, the bigger the mask data and the longer and more expensive the mask; the more conditions it's checked under, the longer the computers have to run. But a pattern that is only right under ideal conditions can fail in production. If the tape-out date were tight, which layers and which places would you spend the time on, and why?
- One spot on a mask prints in every field, so masks are taken down and inspected after a while. Check too often and the mask spends more time out of use; check too rarely and a problem may only be found once it has grown. If you set the schedule, how would you balance it, and what would you look at?
Part 3: Inside the fab
How a wafer becomes chips step by step: what each step does, why it is done that way, and what goes wrong if it isn't.
Unit 6Wafers and cleanrooms
Chips are made on a round silicon wafer, inside a very clean cleanroom. Why round? Why ever larger? And how clean is clean enough?
Goals
- Explain why wafers are round, what 12-inch and 8-inch mean, and what larger wafers gain.
- Describe cleanroom classes by the most particles a cubic meter of air may hold, and why a single particle can ruin a chip.
- Know that a fab also uses large amounts of ultrapure water and special gases, and why they are handled so carefully.
- ReadWhy are wafers round?What do 12-inch and 8-inch wafers mean, and why did wafers get bigger?How clean is a cleanroom? What Class 100 and ISO 5 mean
- FurtherWhat is a bunny suit, and why do chip fab workers wear one?How pure is ultrapure water, and why do chip fabs use so much of it?What gases does a chip fab use, and why so much care?Why do semiconductor fabs use so much electricity?
- LookAir shower · Gas cabinet
- PlayPlay a shift as a facilities engineer: water, power, air and gases
Think
- A fab uses a lot of water and electricity, and it matters to the economy. If you lived near one, what would you care about? What would you ask the company to explain?
- In a cleanroom, people are the biggest source of particles. If you wrote the rules for going in and out, which three rules would you set, and why?
Unit 7How chips are made: the big picture
A wafer goes through hundreds of steps over several months in a fab. Look at the whole map first; the next units zoom in one area at a time.
Goals
- Outline the rough order a chip goes through: design, photomasks, the fab, testing and packaging.
- Say what each of the fab's seven process areas does: wet clean, furnace, thin film, litho, etch, CMP and implant.
- Explain that a chip is built up layer by layer: deposit a material, print a pattern, remove what is not needed, and repeat many times.
- ReadHow are computer chips made? The semiconductor manufacturing process, step by stepWhat do the seven process areas of a chip fab do?
- FurtherWhat is a wafer start, and why does a fab count from that day?What is a fab in semiconductors, and what does "going into the fab" mean?What is a recipe in semiconductor manufacturing?
- LookCluster tool
- PlayStart at chapter 2, "Station by Station": one hands-on step in each of the seven process areas
Think
- Why is a chip built by repeating "deposit, print, etch" layer after layer rather than all at once? Try explaining it with house building or another everyday example.
- A wafer spends months in the fab. Over such a long process, where do you think the biggest risk lies, and how could it be caught early?
Unit 8Wet clean: washing wafers between steps
Every step leaves something invisible on the wafer surface, and the next step needs a clean surface. Cleaning is one of the most repeated steps in the whole flow: clean too little and the next layer grows badly; clean too much and what's eaten away can't be put back.
Goals
- Name the four kinds of things a wet clean removes, and what each one does if it stays.
- Explain the stages of the common standard clean and what each one removes, why every chemical is followed by an ultrapure-water rinse, and what tank-by-tank batch cleaning and one-wafer-at-a-time spraying are each good at.
- Explain how concentration, temperature and time set how hard a clean works, why cleaning too long is a problem too, and why a cleaned wafer can't wait long.
- ReadWhat is wafer cleaning, and why are wafers cleaned so many times?
- LookBatch wet bench
- PlayPlay a shift as a wet clean process engineer: the bath, the soak time and how long a cleaned wafer can wait are yours
Think
- A batch tool cleans many wafers at once; a single-wafer tool cleans one at a time and is less likely to carry dirt from one wafer to the next. If you had to choose one for a certain step, what would you ask first?
- A cleaned wafer has a time limit, but the next tool may go down, be in maintenance, or have hot lots queued ahead. Should the next lot be cleaned now? What does each choice cost?
Unit 9Furnace: oxidation and annealing in the heat
In many processes, the very thin insulating layer under a transistor's gate is grown in a furnace, and implanted atoms only start to conduct after heating. But every heating moves what was made before a little more, so the heat has to be counted from start to finish.
Goals
- Explain why thermal oxidation needs high heat, where the new oxide grows, and what dry and wet oxidation are each used for.
- Explain how annealing makes implanted atoms conduct, what too much or too little temperature and time do, and why some anneals now heat for only seconds.
- Describe how a furnace heats a hundred-plus wafers alike (heating zones, dummy wafers) and how that is checked (monitor wafers), and why the thermal budget is planned from start to finish.
- ReadWhat does a furnace do in a chip fab? Oxidation and annealing explained
- LookVertical furnace
- PlayPlay a shift as a furnace process engineer: a hundred-plus wafers a load, and the temperature and time are yours
Think
- A furnace load of a hundred wafers is efficient, but if that load goes wrong, the loss is large too. In your own life or work, when would you do many at once, and when would you rather do one at a time? Why?
- A furnace run stops halfway. Rerunning the whole step spends a whole extra step's worth of thermal budget; holding the lots, measuring the monitor wafers and running only what's left takes more time. If it were your call, what would you want to know first?
Unit 10Thin film: building up layer by layer
Almost every layer of a chip starts with a new film of material, so that there is something to print and etch. How thick, how even and how clean the film is carries on into etch, polishing and the next litho step.
Goals
- Say what a thin film is, why almost every layer starts with one, and how it differs from oxidation in a furnace and from epitaxy, which follows the wafer's crystal grid.
- Tell where the film comes from in CVD, sputtering and ALD and what each is good at, and explain why many tools pump down to a vacuum first and why the opening of a deep hole closing first is a problem.
- Explain why a film has to be even, free of particles and must not bend the wafer too much, and how it is measured afterward.
- ReadWhat is thin film deposition? How chips are built up layer by layerWhat is epitaxy? How a perfectly ordered layer of silicon grows on a wafer
- FurtherWhy do semiconductor tools need a vacuum?
- LookCVD chamber · PVD chamber
- PlayPlay a shift as a thin-film process engineer: look after every film your sputtering tool lays down
Think
- Which do you think is harder to control, how thick a film is or how even it is? If it is thicker in the middle than at the edge, what problems might later steps run into?
- A film a little thicker or thinner changes what comes out of CMP, the next step. If you were the thin-film engineer, what would you tell the next step before they ask, and why?
Unit 11Lithography: printing the pattern
Lithography (litho) decides how fine a chip's patterns can be. It is one of the most precise steps, and the most advanced lithography machines are extremely expensive.
Goals
- Explain what photoresist, a photomask, exposure and development each do, using the analogy of printing a photo or using a stamp; tell positive from negative resist, and say why the litho area is lit yellow.
- Explain how a layer is aligned to the one below before exposure, how overlay is measured after printing, how the measured error is corrected on the next lot, and why a layer can still be redone before etch.
- Explain why shorter wavelengths of light can print finer patterns, how 193 nm light prints lines a few tens of nanometers wide, and why extreme ultraviolet (EUV) is so hard to do.
- ReadWhat is photolithography? How do chip patterns get printed?What is photoresist? How are positive and negative resists different?What is overlay? Why does each layer of a chip have to line up with the one below?Why is the lithography area in a chip fab yellow?
- FurtherHow does 193 nm light print lines only tens of nanometers wide? Immersion lithography and multiple patterningWhat is extreme ultraviolet (EUV) light, and why is that machine so hard to build?
- LookCoater/developer · Scanner
- PlayPlay a shift as a litho process engineer: printing circuit patterns onto wafers
Think
- Before the next layer is printed, it has to be aligned to the one below; a tiny miss can ruin the whole wafer. What in your own life has to line up with the layer before it? What happens if it's off, and how would you check that it lines up?
- The most advanced lithography machines are extremely expensive. What might a machine that costly mean for the price of chips, and for who can afford to make the most advanced ones?
Unit 12Etch: cutting the pattern in
Litho only prints the pattern onto the photoresist; the material underneath hasn't been touched yet. Etch is what really cuts the pattern into the wafer, and a mistake there is hard to undo.
Goals
- Explain how etch relates to litho: how the resist works as a stencil, and why etch removes only what it doesn't cover.
- Tell wet etching from dry etching, say what plasma is and why it cuts both straight and selectively, and what selectivity is.
- Explain how a tool knows it has etched through, why it etches a little longer, what too little or too much does, and why the chamber needs watching every day.
- ReadWhat is etching? How are dry and wet etching different?What is plasma, and why do chip fabs etch with it?
- LookPlasma etch chamber
- PlayStart at chapter 6, "The Call": the etcher stops in the middle of the night
Think
- Endpoint detection says the layer is through, yet the tool keeps etching a little longer: too short and some holes don't open, too long and the layer below is damaged. If you had to set how long, what data would you look at first?
- A tool fails at night with a wafer stuck inside, half etched. What does waiting for more information cost, and what does acting right away cost? (Think about it after playing chapter 6.)
Unit 13Doping: ion implant and annealing
Very pure silicon barely conducts. A chip needs "this small region conducts, the one next to it doesn't", so a tiny amount of other atoms has to go into the right places, at the right depth.
Goals
- Explain why pure silicon barely conducts, how n-type differs from p-type, and how n and p are laid out so a switch stays off until a voltage on its gate turns it on.
- Explain how an implanter drives atoms into silicon, what the energy and the dose each decide, and how photoresist blocks the places that shouldn't be implanted.
- Explain why the wafer is annealed afterwards, why a wrong implant can't be saved, and why the settings are checked before the run and the sheet resistance measured after.
- ReadWhat is doping? How n-type and p-type silicon make a switch that's normally offWhat is ion implantation, and how does a fab shoot atoms into silicon?
- LookIon implanter
- PlayPlay a shift as an implant process engineer: the atom, the energy and the dose are yours
Think
- A wrongly implanted wafer looks exactly like a good one and may not be caught for a long time. If you were the one checking line by line before the lots go in, how would you make sure you don't miss a line? Who should check it again with you?
- An anneal has to be hot enough, but not too long. When "a bit more is safer" and "too much does harm" are both true, how would you decide where to stop?
Unit 14Wiring and polishing: CMP and layer upon layer of metal
Transistors are only useful once layers of metal wiring connect them. How the wiring is dug, filled with copper and polished flat decides whether current gets through, and how fast the chip runs.
Goals
- Explain why a chip is like a building: transistors at the bottom, layer upon layer of wiring above, joined up and down by vias and contacts.
- Explain why copper is dug first and filled after (damascene), why a barrier layer goes in first, and why copper-touched tools and wafers are kept apart from the front end.
- Explain why CMP polishes flat, where it stops, what goes wrong with too little or too much, and why wiring is slowing chips down more and more.
- ReadHow is the wiring inside a chip made? Vias, copper, and why the trenches come firstWhat is CMP, and why do wafers need to be polished flat?
- LookChemical mechanical polishing
- PlayPlay a shift as a CMP process engineer: deciding how much to polish and where to stop
Think
- A polishing pad gets smoother with use, so the same time removes less and less. What does stopping for two hours to change the pad cost, and what does lengthening the polish time to get by cost? Who is affected either way?
- The film from the step before came out a little thicker, still within spec, and what CMP polishes off changes with it. Between the two steps, who should notice first, and who should speak up first?
Unit 15Process integration: putting hundreds of steps in order
Every step can be done right and the chip still may not work: hundreds of steps have to be put in one flow, and someone has to watch how they affect each other from start to finish.
Goals
- Tell in order how one transistor is made (isolation, wells, gate, source and drain, anneal, contacts, the first metal layer) and why each step is needed.
- Explain why the order can't be changed at will (metal can't take high heat, and heat adds up), and why some steps can't wait long between them (Q-time).
- Explain how a chip can come out wrong even when every step is within spec, and how an integration engineer works back from the result.
- ReadHow is a transistor made? From isolation to the first metal layer, step by stepWhat does a process integration engineer (PIE) do, and how is it different from a process engineer?What is Q-time, and why can't wafers wait?
- PlayPlay a shift as a process integration engineer: you look after not one tool but a product, from the first step to the last
Think
- Changing one condition makes this step better but may make a later step worse. Who should have the say over whether to change it? What data should they see before deciding?
- The tool at the next step suddenly stops while a lot's Q-time is counting down. What does waiting for the repair cost, and what does redoing the step before cost?
Unit 16A factory that never stops
A fab never turns off the lights: wafers ride in sealed boxes along tracks in the ceiling, some steps cannot wait too long between them, and hot lots and machine maintenance all have to fit in.
Goals
- Explain why a fab runs 24 hours a day, and what stopping would cost.
- Describe how wafers move around a fab and how MES keeps track of where every lot is, and why one wafer takes months to finish.
- Understand the trade-offs in scheduling: how hot lots, time limits between steps (Q-time) and maintenance affect each other.
- ReadWhy do chip fabs run 24 hours a day?How do wafers move around a fab? FOUPs and the overhead hoist transportWhat is MES, and how does a chip fab know where every lot of wafers is?How long does a wafer take to make, and why does cycle time run to months?
- FurtherWhat is a hot lot, and why doesn't it always go first?What do the red, yellow and green lights on a tool mean?
- LookOHT · stocker
- PlayPlay a shift in Manufacturing: keeping a whole area's lots moving
Think
- Shift work keeps the factory running, but people need sleep. How should a factory that never stops look after the people who work in it?
- When a hot lot jumps the queue, the lots in front have to wait. Should hot lots always go first? Who decides, and on what basis?
Part 4: How do you know it was done right?
How a fab measures, watches its numbers every day and counts its yield, and how it deals with a problem step by step.
Unit 17Metrology and inspection: what to measure, and how many wafers
A wafer goes through hundreds of steps over weeks to months before it can be powered up and tested. Finding a mistake only then is far too late, so each important step is checked as soon as it is done.
Goals
- Explain why a fab can't wait until a wafer is finished to check it, and measures halfway through instead.
- Tell metrology from inspection, say roughly how film thickness, line width and overlay are measured, and how defect inspection differs from defect review.
- Explain why most measuring and defect scanning is sampling plus monitor wafers, and what measuring more, or less, costs.
- ReadHow does a chip fab know each step went right? Metrology vs inspectionWhat is wafer defect inspection, and how do fabs find particles and scratches?
- LookMeasuring electron microscope
- PlayStart at chapter 2, "Station by Station": on day 2, go to the metrology tool and measure the monitor wafers from the furnace load
Think
- Measuring more is reassuring; measuring less keeps lots moving. If a tool you look after has been a little unsteady lately, how would you decide how many more lots to measure? Who would you talk to first?
- "Compare with the chip next door" can't find a problem every chip shares. In your own life or work, is there a mistake you can't see because everything has it? How would you find it?
Unit 18Control charts and daily monitoring
A measured number only means something next to a yardstick that says whether the process is still behaving as usual. The control chart is that yardstick: it shows a process changing before anything has been made wrong.
Goals
- Explain where control limits come from and how they differ from spec limits, and tell OOC from OOS.
- Explain why a fab may stop and look for a cause even when everything is within spec, and even when no point is outside the limits.
- Say what monitor wafers, FDC and APC each look at and when, and why a system correcting every lot by rules does not clash with "leave it alone inside the limits".
- ReadWhat is an SPC control chart, and how are OOC and OOS different?What are monitor wafers and dummy wafers, and how does a fab tool prove it's still OK?What is APC? How a chip fab corrects itself after measuring: feedback and feedforwardWhat is FDC? How a chip fab keeps watch on its tools' sensors
- FurtherWhat is PM (preventive maintenance), and why do fab tools stop on a schedule?What is change control in a chip fab, and why does one change need so many sign-offs?
- PlayStart at chapter 7, "Firefighting": OOC lots wait in your inbox, and a control chart on the metrology tool has 8 points in a row below the center line
Think
- The control chart says "still within spec, but no longer normal", and the lot is waiting. If it goes on to the next step, who pays? If it stays held, who pays?
- Control chart rules and FDC thresholds catch problems earlier the tighter they are, and raise more false alarms too; set them too loose and slow decline goes unseen. If you were setting them, where would you draw the line? Will someone called out by false alarms many times still look carefully next time?
Unit 19Yield and wafer maps
What a fab finally hands over is good chips. Yield says what share is good, a wafer map says where the bad ones are, and only the two together tell you which step to go back and look at.
Goals
- Explain how yield is calculated, why tiny losses at each step multiply into big ones, and, using defect density, why bigger chips have lower yield.
- Tell WAT from a wafer map: one measures test keys in the scribe lines, the other tests every single chip.
- Say what kind of problem a shape of failures on a wafer map often points to, and explain how a new process's yield climbs round by round (yield learning) and why the climb slows.
- ReadWhat does "yield" mean in chip news, and why does 1% matter so much?Why do bigger chips have lower yield? Defect density, yield models and how yield improvesWhat is WAT, and how does a wafer map show what went wrong?
- PlayStart at chapter 3, "The shape of a failure": one wafer fails WAT, then you point out what is wrong on three wafer maps
Think
- Yield rises from 90% to 95%. What does that mean for the fab, for the company buying the chips, and for the people using the product?
- Failures on a wafer map form a grid: it could be the mask, or it could be the probe card. How much effort would each take to check? Which would you check first, and why?
Unit 20When something goes wrong: from the alarm to "never again"
Even the most careful fab has problems. What makes the difference is whether, in those first minutes, things are done in the right order, and whether afterwards the holes that let the mistake through get closed.
Goals
- Give the order of what happens after a problem appears: stop it and contain it first, then confirm, draw the boundary, decide wafer by wafer what happens to them and look for the cause, and explain why it goes in that order and who usually decides.
- Explain why an OCAP (out-of-control action plan) is written in advance, and what happens when it doesn't cover the case.
- Explain how the 5 Whys follow a root cause down to a layer that can be changed, why a review looks for holes in the process rather than for who was careless, which kind of countermeasure is the most reliable, and why a case is closed only on evidence.
- ReadWhat does OCAP mean in a chip fab?What is a lot hold, and who decides whether to release, rework or scrap?What is root cause analysis, and how do 8D and the 5 Whys work?
- FurtherWhat is failure analysis (FA), and how do engineers find out why a chip failed?What does MO mean in a chip fab?
- PlayStart at chapter 8, "In a Hurry": redo the wafer stuck overnight, then close the holes in the process at the review
Think
- At three in the morning a tool lights red, a lot is waiting, the engineer is asleep, and the person next to you says one reset usually does it. What does calling per the OCAP cost, and what does trying it first cost?
- Think of a small mistake you keep making, such as leaving home without your keys. If you don't blame your own carelessness but look for "what makes this easy to forget", how would you change things so it can't happen or can't be forgotten?
Part 5: After the wafer is finished
Once the wafer leaves the fab: how chips are tested and packaged, how they are shown to last for years and the weak ones screened out, and how they are packed, shipped and soldered onto circuit boards to go into the products in your hands.
Unit 21Packaging and testing
A finished wafer is not yet a usable chip. It is tested, cut apart, connected, sealed in a package and tested again before it goes into a product.
Goals
- Explain the three jobs of a package: protecting the chip, connecting its contacts to the outside, and helping it shed heat.
- Tell wafer sort (CP) from final test (FT): when each happens and what each catches.
- Describe how wire bonding and flip chip connect a chip in different ways, and read what package names like BGA and QFN describe.
- ReadWhat is chip packaging, and why does a finished chip still need a package?How are chips tested, and how is wafer sort (CP) different from final test (FT)?What is wire bonding, and how does a chip connect to the outside?
- FurtherWhat do chip packages look like, and what do names like BGA and QFN mean?What is a probe card, and how does every chip on a wafer get tested?What is flip chip, and how does a chip connect through solder bumps?What is an OSAT, and what happens in a test-and-assembly house?What is SiP? Chips and small parts packed into one tiny module
- LookWafer prober · Wire bonder · Molding machine · Final test
- PlayStart at chapter 11, "The Ball Lifted": two wire pulls test low
Think
- More testing means more reliable chips, but also more cost and time. If you were responsible for a hearing-aid chip, how would you decide how much to test?
- Why do some companies specialize in packaging and testing instead of leaving it all to the fab?
Unit 22Reliability, shipping and building chips into products
Testing only asks whether a chip is good "right now", but it has to work inside a product for years. This unit looks at how a few weeks can tell you about years from now, how weak chips are screened out, and how chips are packed, shipped and soldered onto circuit boards to end up in the products in your hands.
Goals
- Say what a reliability test asks, how accelerated conditions let a few weeks stand in for years, and what each of the common tests checks.
- Read the bathtub curve, tell reliability testing (a sample) from burn-in (every chip), and know why lots with very low yield call for extra care.
- Say how chips go into tape and reel, why moisture-sensitive ones need a dry pack, and how an assembly plant solders them onto circuit boards with SMT.
- ReadWhat is reliability testing, and how can you tell in weeks that a chip will last for years?How are chips shipped? Tape and reel, dry pack and moisture sensitivity levelsHow are chips soldered onto circuit boards? SMT and reflow soldering
- FurtherWhat is burn-in, and why are chips "burned in" before they ship?
- LookReliability oven · SMT line
- PlayStart at chapter 12, "The Night Before Shipping": you decide whether to run a two-day sample for early-life failures or ship tomorrow as planned, then check the dry pack, the last item, in the shipping area
Think
- The batch ships tomorrow morning. The reliability lab offers to take a few hundred chips and run them powered at high temperature for two days to check for early-life failures, but the whole batch would ship a week late. If the decision were yours, what would you want to know first? And who would you talk to first?
- The caution label on a moisture barrier bag is just a few boxes of text: the level, the seal date, how long you have to solder the parts after opening. If you loaded parts onto the machines at an assembly plant, how would you make sure every bag is handled that way? If one box were left empty, who would run into trouble, and when?
Part 6: People and teamwork
Who works in a fab and how the shifts run, and who does what, in what order, as a new chip goes from R&D to mass production.
Unit 23The people in a fab: roles, shifts and careers
A fab is not just machines. This unit looks at its departments, who talks to whom every day and who does what first when something goes wrong, then at the jobs inside and what shift work and being on call involve.
Goals
- Say what Manufacturing, Process, Equipment, Integration, QA, Production control and Facilities each look after, and why every department talks to several others every day.
- Say who does what when something goes wrong: who stops the lot, who finds the cause, who decides on each wafer, who checks the rules were followed and who replans; and tell the work of a process engineer from that of an equipment engineer.
- Look at shifts, on-call duty and working hours through public information: what comes with the job itself, and what differs from company to company.
- ReadWhat departments does a chip fab have, and who talks to whom every day?What jobs are there in the semiconductor industry? From chip design to the fab to testWhat's the difference between a process engineer and an equipment engineer?Is working in a semiconductor fab hard? Shifts, on-call and hours
- FurtherWhat's the difference between a fab technician and an engineer?Which degrees work in a chip fab, and what does each one do there?What does an equipment engineer do in a chip fab?What does the manufacturing department do in a chip fab, and how are lots scheduled?What does QA (quality assurance) do in a chip fab?What does a fab facilities engineer do?Is a PE a process engineer or a product engineer?
- PlayPlay one shift in one role, then the same shift in another role, and compare
Think
- A machine fails in the middle of the night. Who should be woken up? What does waking someone cost, and what does not waking them cost?
- At the same moment, say when a machine goes down, what are process, equipment and Manufacturing each worried about? Which role would you most and least like to have, and why?
Unit 24From R&D to production: who goes first, and how the handoff works
A new chip, from the first time it's made in a fab to steady high-volume shipments, passes through several legs: design, the fab, test, reliability, the customer and the production fab. This is new product introduction (NPI). A new process generation, or a chip that needs new steps, is also often made and made stable on the R&D line first. Each leg is taken over by different people, and how clear the handoff is decides how well the next people can do their job.
Goals
- Say who takes over at each stage of new product introduction (NPI), from tape-out, the pilot run and revisions to reliability tests, the customer's approval and the handover to volume production, and what question the R&D line and the production fab each ask.
- Know what a technology transfer hands over: the standard process (POR), specs, work instructions, training and reliability data.
- Know how Production control, Manufacturing, Equipment, Process and Integration share the work once production starts, and how word passes from one to the next when something goes wrong.
- ReadHow is an R&D line different from a production fab?What does an R&D integration engineer do with a new chip's first lot?What is new product introduction (NPI), and who takes over at each step from a new chip's pilot run to volume production?
- FurtherWhat does production control do in a chip fab, and how are due dates set?What does the customer liaison at a test-and-assembly house do?
- PlayStart at chapter 5, "The Last Box": the standard process goes to the production fab tomorrow, and only one alarm limit is left to fill in
Think
- The reliability tests haven't finished, but the customer wants wafers started in the production fab now (a risk start): if the tests pass, the customer gets parts sooner; if they fail, the lots started early may all be scrapped. In your place, how would you explain the cost of each side to the customer?
- Work instructions are written for someone who may never have trained on the R&D line. How detailed do you think they need to be so that someone following them doesn't go wrong? What can't be passed on in writing alone?
Part 7: The future
How small transistors can still get, and the other roads taken alongside shrinking: changing the transistor's shape, moving power lines to the back of the wafer, stacking upward, joining several chips in advanced packaging, other semiconductor materials, and light to carry data, several of which have to do with the "memory wall" (processors compute fast, but data can't arrive fast enough); and finally how to read chip stories in the news.
Unit 25How small can transistors get? The story of "nanometers"
The news talks about "2 nm" and "3 nm" every day. Once you know where the number comes from, why each shrink gets harder and why transistors keep changing shape, you can see where chips are heading next.
Goals
- Know how small a nanometer is, and that a name like "2 nm" is the name of a process generation, not the length of anything on the chip.
- Explain what Moore's law says, and why shrinking keeps getting harder: atoms, leakage and heat, slower wiring, and rising cost.
- Explain why transistors went from flat to a standing fin (FinFET) and then to a gate wrapped around all four sides (GAA), and why power lines are starting to move to the back of the wafer.
- ReadWhat is Moore's law, and why do people say it's slowing down?What are FinFET and GAA? Why transistors went from flat, to standing up, to surrounded on all four sidesThe news says "2 nm". What exactly is 2 nm?
- FurtherWhat is backside power delivery? Why chips are moving their power lines to the back of the wafer
- PlayPlay a shift as a litho process engineer: look after every layer the scanner prints
Think
- A newer generation usually does the same work on a bit less power, or a bit faster on the same power, but it is also harder and more expensive to make. If you were making a chip that runs on a single button cell, would you go for the newest generation? What would you ask before deciding?
- Process names stopped being real sizes long ago, yet each new one is still roughly the last one times 0.7 (with some half-steps in between). What is good about naming them this way, and what does it lead people to misunderstand? If it were up to you, how would you name them?
Unit 26Advanced packaging and new materials: more than shrinking
Processors compute faster and faster, but memory can't deliver data fast enough to keep up, and this "memory wall" often leaves AI chips waiting. Stacking memory right next to the processor, packaging chips together and sending data over longer distances as light all have to do with it; add new materials, and once you know these roads, the new terms in the news start to fit together.
Goals
- Explain what the memory wall is: why the processor so often stops to wait for data, why moving data costs more energy than computing, and why AI hits the wall hardest.
- Explain what cache, HBM, chiplets, 2.5D and 3D each do, and know that these roads can be used together and that each has a price.
- Tell which problem wide-bandgap materials and silicon photonics each solve, and know that neither is about replacing all silicon or all copper wiring.
- ReadWhat is the memory wall, and why can't data keep up with fast chips?The news says "advanced packaging". What is it, and why do chips sit side by side or stack up?The news says "HBM". What is it, and why does AI need special memory?
- FurtherThe news says "wide-bandgap semiconductors". What are SiC and GaN?The news says "silicon photonics". What is it, and why send data with light instead of electricity?
- PlayStart at chapter 11, "The Ball Lifted": walk the assembly line with Shu-Hui and watch the chip go into one small module along with resistors and capacitors
Think
- Splitting a big chip into chiplets may improve yield and put the money where it matters most; but it needs extra room for connections, the packaging gets harder, and if one piece inside is bad, the whole set is wasted. If it were up to you, what kind of chip would be worth splitting? What kind would you keep in one piece?
- To get past the memory wall, you can add more cache or put more HBM stacks beside the processor, and some researchers are working on computing inside the memory; every road has a price. If you were building a machine that only answers questions with AI, which road would you spend money on first? What would you want to know before deciding?
Unit 27Making sense of chip news
"Mature-node shortage", "AI chips", "a major breakthrough": with what you have learned so far, you can read these headlines and spot where they jump too fast.
Goals
- Explain how mature nodes differ from advanced nodes, why older generations still matter and cost less, and why the news so often swings between shortage and oversupply.
- Explain why an AI chip packs in so many simple calculating units, and how chips for training and for inference differ.
- Tell apart "made in research", "in mass production" and "widespread" in the news, and explain why a new technology often takes ten years or more to go from a paper to mass production.
- ReadThe news says "mature nodes". Why do older chips still matter?The news says "AI chips". What are they, and how are they different from ordinary processors?How long does a new chip technology take to go from a paper to mass production?
- FurtherThe news says "automotive chips". What makes them different?
- PlayPlay a shift as the furnace R&D process engineer on the R&D line: the game's hearing-aid chip, Glowmere, isn't made on the newest generation, yet its furnace conditions still have to be settled on the R&D line
Think
- Find a recent chip news story and retell it to someone at home in three plain sentences. Which words did you learn in this course? How far along is what it describes: made in research, in mass production, or already widespread? Which claims seem exaggerated or unclear?
- What kind of chips do a car, a phone and an AI server each need? If you could add only one more production line, which would you build it for first? Why?
Suggested assignments (open-ended, no single right answer)
- The life of a chip: draw a flow chart from design to finished product. Mark the three places you think are most likely to go wrong, and the step at which a problem there is usually discovered.
- A handover note: after playing a shift, write a handover note for the next shift: what happened, what you decided, and what is still open. Swap with a classmate and see whether they could carry on from it.
- Chip news in plain words: rewrite a chip news story in three plain sentences for someone who has never studied this, and mark anything in the original that seems exaggerated or unclear.
- Same moment, different people: in groups, each member plays the same shift in a different role. Compare what each role saw and feared when the machine went down, and write it up in one page.
- Find the simplification: pick a passage from a required article, compare it with a textbook or university lecture notes, and write down what the article simplified and whether the simplification is reasonable.
Level and accuracy
No physics or chemistry background is needed; middle-school science is enough. The aim is to understand the flow, the division of labor and the trade-offs, not to learn to operate machines.
The articles are written from public textbooks, industry standards, university course notes and papers, and checked again after writing. To stay readable, some things are simplified: analogies instead of equations, and "about" in front of many numbers. To go further, pair them with two kinds of textbook: semiconductor devices (why it works) and semiconductor manufacturing processes (how it is made). If you spot a mistake, use "Spot a mistake? Report it" at the end of each article.
The companies, people, machine numbers, lot numbers and figures in the game are fictional, do not represent any company's actual practice, and are not operating training. What is real is the shape of the work: shifts, handovers, time limits between steps, test runs, and following procedures when something goes wrong.
Citing and classroom use
This outline, the articles, the machine clips and pictures, and the worksheet are free to use in class and for non-commercial teaching: on screen, in handouts, printed for students. Please credit fab24hr. Do not sell them or present them as your own work.
To cite it, for example: "Semiconductors 101: a free course following the life of a chip." fab24hr, October 2026. https://fab24hr.com/en/learn/
To use the game in a single lesson: fab24hr in the classroom has 20-, 40- and 50-minute plans; the worksheet prints as it is; Chip fab machines, taken apart links to all 31 machines, with QR codes.
Questions people ask
Is this a formal course? Does it cost anything or need sign-up?
No cost and no sign-up. It is a free syllabus: each unit links to plain-language articles on this site and a chip fab game that runs in the browser, and most units on the fab and on packaging and testing also link to 3D machines you can take apart. There are no exams or certificates, and teachers can change the order and the amount to fit their course.
Can I follow it without a science background?
Yes. The articles are written for complete beginners, every piece of jargon is explained in plain words, and middle-school science is enough. The aim is to understand the flow, the division of labor and the trade-offs; to go further, add textbooks on semiconductor devices and on manufacturing processes.
Is it available in other languages?
Yes. This outline, the articles and the game are in Traditional Chinese, English and Japanese: the Chinese version is at fab24hr.com/learn/ and the Japanese one at fab24hr.com/ja/learn/.
- What is fab24hr?: the two ways to play, the four shifts, common questions, sources
- The life of a chip: the life of one chip: tape-out, pilot run, mass production, wafer test, packaging, shipping
- A day in the life of a fab engineer: who does what (PE, EE, PIE, manufacturing), and the day hour by hour
- Who works in a chip fab: technicians, Manufacturing, process, equipment, Facilities, integration, QA, production control, masks, R&D, the chief, the vendor, and test and assembly at the test-and-assembly house: each role's day
- Chip fab jargon in plain English: MO, Hold, Q-time, OCAP and the rest, one plain sentence each
- Chip fab machines, taken apart: What 31 chip fab machines do (etch, scanner, CMP, furnace, packaging…), each as a 3D model to take apart
- fab24hr in the classroom: Semiconductor lesson plans: 20/40-minute plans, a lesson per chapter or process area (3D machines, the game, articles), discussion questions, a worksheet, FAQ
- About and press kit: trailer, gameplay clips, descriptions and key facts
- fab24hr Blog: Semiconductors, how chips are made, fab life, packaging, words from the news: plain-English articles by topic
Latest
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- What does it take to build a chip fab, and why does it take years and so much money?
- What is electrostatic discharge (ESD), and why are chips so sensitive to static?
- What is MEMS? How do you build tiny moving machines on a chip?
- What is the semiconductor cycle? Why do chips swing from shortage to oversupply?
- What is a power semiconductor? The chips that handle high voltage and big currents
- What is a TSV (through-silicon via), and how do stacked chips connect straight through?