What are FinFET and GAA? Why transistors went from flat, to standing up, to surrounded on all four sides

FinFET and GAA are two shapes of transistor. A FinFET (fin field-effect transistor) stands the channel, where the current flows, up on its edge as a tall, thin "fin", and the gate grips it on three sides: the top and both sides. GAA stands for gate-all-around: the channel becomes a few thin sheets stacked on top of each other, and the gate wraps around every sheet, top, bottom and both sides. Both changes of shape had the same goal: keeping very small transistors able to shut tightly.

What does the gate do?

A transistor is a tiny switch run by electricity (see What is a transistor?). Current flows from the entrance (the source) through the channel to the exit (the drain), and the gate over the channel works like the handle on a tap: put a voltage on it and the channel opens; take it away and it closes.

Why did flat transistors stop shutting tightly?

Transistors used to be flat: the channel lay on the silicon surface, with the gate only on top. As they shrank, the source and drain moved closer and closer, and a gate on top could control the top of the channel but not the bottom. Even when the gate said "off", a little current slipped through. That's leakage. Add up more than ten billion transistors and your phone uses power while it sits idle (see Why do chips use power?).

FinFET: stand the channel up

The channel is stood up as a very thin wall, like the fin on a fish's back. The gate is like an upside-down U that straddles the fin and grips the top and both sides at once. The fin is only a few nanometers wide, so squeezed from both sides, the whole channel is under control and it shuts much more tightly.

Standing it up has another benefit. The "width" the current can use is roughly both sides of the fin plus the top. Make the fin taller and it takes up no more space, but it carries more current; a transistor that needs more current gets two or three fins side by side.

Transistors like this came into wide use around the early 2010s. The name was given by a university research group around 2000, and it took more than ten years to go from paper to mass production (see How long does a new chip technology take to go from a paper to mass production?).

How is a FinFET made, step by step?

The main line is the same as for a flat transistor: keep them apart, make the bases, make the gate, make the entrance and exit against the gate, then connect the wiring (see How is a transistor made?). What's new is carving the fins first, and the gate often starts out as a stand-in. A simplified, general version:

1. Carve the fins: print rows of very fine lines on the silicon and etch down, leaving rows of fins. The fins are finer than a lithography tool can print in one exposure, so methods such as multiple patterning are often used (see How does 193 nm light print lines only tens of nanometers wide?). If fins come out wider, narrower, taller or shorter, every transistor's current differs.
2. Isolate, then reveal the fins: fill the spaces between fins with oxide, polish it flat with CMP, then etch the oxide back down so the top part of each fin sticks out. The buried part keeps the transistors apart; the part that sticks out is the channel. If the etch-back is uneven, fins stick out by different heights and carry different currents. Then, as with flat transistors, atoms are shot in to make the n-type and p-type wells.
3. Lay a stand-in gate across the fins: deposit a layer of polysilicon, pattern it into lines that cross the fins, and build insulating sidewalls on both sides. This marks where the gate will be. The real gate materials can't take the high temperatures to come; put them in now and later heating steps would ruin them.
4. Grow the source and drain: cut back the fin on both sides of the gate and regrow it by epitaxy as heavily doped silicon or silicon-germanium (silicon with some germanium mixed in), then heat it so the atoms settle in. This lets current flow more easily (see What is epitaxy?). Every heating step adds to the thermal budget: too much heat and the atoms drift sideways, blurring the shape.
5. Swap in the real gate: cover with insulator, polish down until the stand-in gate shows, remove it, and line the trench it leaves with a very thin new insulating material and metal that wraps the fin on three sides. If the trench isn't filled completely, the gate can't control the whole fin.

The contacts and wiring above it are the same as for a flat transistor (see How is the wiring inside a chip made?).

Why weren't fins enough anymore?

Fins are already only a few nanometers thin and hard to make thinner, and as the gate gets shorter, gripping three sides still can't quite control the very bottom. Fins also come in whole numbers, so a transistor's current can only be set to one, two or three times one fin, never one and a half.

GAA: the gate wraps all four sides

GAA lays the fin on its side: the channel becomes a few sheets stacked one above another, each only a few nanometers thick. The gate fills the gaps between them too, so it surrounds every sheet on all four sides. These are called nanosheets; narrower ones, more like thin wires, are called nanowires.

The width of a sheet is printed, so a switch that needs a lot of current gets wider sheets, and one meant to save power or space gets narrower ones. Mass production only began in the 2020s, around the generations the news calls 3 nm and 2 nm, and different makers switch at different times. "So many nanometers" is the name of a generation, not the size of a sheet (see The news says "2 nm". What exactly is 2 nm?).

How do you make sheets that hang in mid-air?

Silicon can't be grown in mid-air, so you first build in "spacers that will be removed later":

1. Grow two materials in turns: by epitaxy, grow a layer of silicon-germanium, then a layer of silicon, and repeat for several pairs. Silicon-germanium's atoms are arranged much like silicon's, so each layer can grow on the crystal pattern below; but chemically it's different enough to be removed on its own later. With a material that doesn't fit, the layers either wouldn't grow neatly or wouldn't come out cleanly.
2. Cut into strips, add a stand-in gate, grow the source and drain: much like steps 1 to 4 of the FinFET, except what you carve is the whole stack. While cutting back for the source and drain, the silicon-germanium is also eaten in a little from the side and filled with insulator, making tiny sidewalls between the sheets; without them, the next step could eat into the source and drain.
3. Remove the silicon-germanium: take out the stand-in gate and use an etch that eats silicon-germanium but barely touches silicon to hollow out the layers in between. The silicon sheets that remain are held at both ends by the source and drain, like the rungs of a ladder. Leave some behind and the sheets differ; etch too far and a sheet thins or breaks.
4. Fill the gaps with the gate: with atomic layer deposition, which adds at most one layer of atoms per round (see What is thin film deposition?), coat each sheet all around with a very thin insulating layer, then fill with metal. The gaps are only a few to a dozen or so nanometers; leave one unfilled and that sheet has a side the gate doesn't control.

What makes GAA hard?

Hollowing out and filling are the hard parts: both happen in gaps only a few nanometers wide, and every sheet has to come out the same. Then there's measuring: the parts that matter most are buried inside the stack where you can't see them from above, and optical measurements aren't sensitive enough to catch small leftovers. X-rays are often used, or a wafer is cut open as a cross-section and examined by TEM, which means that wafer can't be used again (see How does a chip fab know each step went right?).

Next: stacking upward

Both of the following are still at the research stage:

• Stacking the n and p switches on top of each other: chip switches mostly come in pairs of the two kinds (see What is CMOS?), which today sit side by side. Stack them and more pairs fit in the same space. Researchers often call this a CFET (complementary FET).
• Using 2D materials for the channel: thin silicon below a few nanometers and electrons move through it less and less easily. In materials such as molybdenum disulfide, a single layer is only a few atoms thick, and it still conducts that thin. The hard parts are growing them equally well across a whole wafer and making good connections to metal.

There are two ways to stack, and each is hard in a different way. One approach builds the whole stack at once and then makes the top and bottom separately; the taller the stack, the harder it is to etch and fill. The other finishes the bottom layer first, then lays a layer of silicon on top for the upper layer. But some transistor steps run above a thousand degrees Celsius, which the finished bottom layer can't take (thermal budget), so research often keeps the upper layer below about five hundred degrees. Public technology roadmaps mostly place both paths in the 2030s or later, and the years differ from one estimate to another.

In fab24hr

There are no fin or gate-all-around transistors in the game. The fictional hearing-aid chip Glowmere in the main story, The life of a chip, uses a mature process generation, not the smallest transistors. But "doesn't shut tightly, so it leaks" comes up everywhere: in chapter 1 you decide which wafers get transistors made deliberately fast or slow (the corners), and the fast ones leak the most; in chapter 10, Standby Current, the test engineer decides how much leakage gets a chip stopped.

A day in the fab has it too: tap "Clock in", choose "A day in the fab", then on the "Your role today" card tap "R&D line", swipe to the R&D process engineer and tap the Furnace area. In the afternoon shift you choose the heating conditions on the R&D line's only furnace: give it too much heat and the implanted atoms sink too deep, and the short transistors don't shut tightly. The companies, chips, people and numbers in the game are fictional; FinFET and GAA are described from public, general sources, simplified. For other jargon, see Chip fab jargon in plain English.