How is a transistor made? From isolation to the first metal layer, step by step

A transistor is made on the surface of a silicon wafer in this order: dig shallow trenches and fill them with an insulator to keep each transistor apart (isolation); shoot in atoms to make n-type and p-type bases for them (wells); grow a very thin insulating layer and build a gate on it; use the gate itself as a shield to make the source and drain on either side; heat the wafer so the atoms settle in (anneal); cover it with insulator, open small holes and fill them with metal (contacts); and connect the first metal layer. Most steps use several process areas.

This article uses the simplest, flat transistor to show the idea, and it is simplified: a real flow has many more steps. For what a transistor is in the first place, read What is a transistor?

What does a finished transistor look like when you cut it open?

Cut a finished chip open from the side and look at the cross-section. From the bottom up, roughly:

• Inside the silicon: a p-type well and an n-type well side by side, with shallow trenches full of insulator buried between the transistors.
• Each transistor: a gate lying on a very thin insulating layer; the silicon on either side of the gate is the source (the entrance) and the drain (the exit).
• Above the silicon: a thick insulating layer with tiny metal posts standing in it, reaching down to the transistors and up to the first layer of metal wiring.

There are two kinds of transistor, one sitting in a p-type well and one in an n-type well, used in pairs (see What is CMOS?).

Why can't it be made in one go? Each pattern is a full round

A fab can't work on just one small patch: films grow over the whole wafer, and implant hits the whole wafer. To make something happen only in certain places, you first print a stencil, and that takes a full round:

1. Grow a layer of material (thin film or furnace), and polish it flat with CMP if needed.
2. In litho, coat photoresist, expose it through a photomask and develop it, so the pattern is printed in the resist; if it's wrong, it can still be washed off and redone.
3. Etch along the resist pattern, or use the resist as a shield for ion implantation.
4. Strip the resist, clean, measure.

A university textbook published in 2000 teaches with a simplified CMOS flow, and even that needs more than a dozen photomasks and over a hundred steps to reach the second metal layer. Chips made today take far more: a wafer comes back to litho dozens of times, adding up to hundreds of steps. For what each area does, see What do the seven process areas of a chip fab do?

How is a transistor made? Seven steps

Step 1: Isolation, digging trenches between transistors and filling them

• What: Grow a thin oxide as a cushion, cover it with a hard layer of silicon nitride, and print where the transistors will stay; everywhere else, dig shallow trenches into the silicon and fill them with oxide. After polishing flat, strip the nitride off.
• Why: Transistors are packed tightly, and each one needs an insulating wall around it so current doesn't wander into the next.
• Otherwise: Neighboring transistors leak into each other, and the switches don't turn off cleanly.
• Areas: Wet clean, furnace, thin film, litho, etch and CMP. The very first step already goes through six areas.

Step 2: Wells, shooting in atoms to make n-type and p-type bases

• What: Cover half the wafer with resist and implant phosphorus to make the n-type well; switch to another stencil and implant boron to make the p-type well; then heat in the furnace.
• Why: The transistor whose entrance and exit are n-type has to sit in a p-type well, and the p-type one the other way round. With silicon of the opposite type in between, no current flows until the gate voltage opens the way (see What is doping?).
• Otherwise: Without a well of the opposite type, the entrance and the exit are connected all the time, and the switch can't turn off. Get it wrong and the switch won't behave as designed, and atoms that went in can't be taken out.
• Areas: Litho, implant, wet clean, furnace.

Step 3: The gate, a very thin insulating layer plus a gate on top

• What: Grow a very thin oxide in the furnace as the insulating layer, lay down a layer of polysilicon that conducts, then print the gates as thin lines and etch away the rest.
• Why: The gate controls the channel below with its voltage, through the insulating layer. How wide the gate line is printed sets roughly how far apart the entrance and the exit are, so this layer has to be printed especially fine and especially accurately.
• Otherwise: An insulating layer that is too thin leaks, and one too thick makes the switch slower; a gate line too wide is slower, and one too narrow doesn't close tightly.
• Areas: Wet clean, furnace, thin film, litho, etch.

Step 4: Source and drain, with the gate as its own shield

• What: Cover the other kind of transistor with resist, then implant atoms into the silicon on either side of the gate. The gate blocks the area right under it, so the entrance and the exit end up exactly against its two edges. This is called self-alignment.
• Why: Print a separate pattern to line them up and it will always be off a little; with the gate as its own shield, they always line up. The idea dates from the 1960s.
• Otherwise: If they're out of line, a gap opens between the entrance or the exit and the channel, and current can't get through.
• Areas: Litho and implant. Many flows also implant once shallowly first, build a ring of insulating spacers on the sides of the gate, then implant deeper, so the part next to the channel is lighter and lasts longer; that uses thin film and etch too.

Step 5: Anneal, heating so the atoms settle in

• What: Heat the wafer so the implanted atoms take the places of silicon atoms and the disturbed crystal lines up again.
• Why: Freshly implanted atoms are mostly stuck in the gaps and don't conduct yet.
• Otherwise: Too little heat and the sheet resistance stays high; too much and the atoms drift sideways, blurring the shapes that were just aligned. So a quick method that heats for only a few seconds is common, and every heating counts against the thermal budget.
• Areas: The furnace, or a quick-heating tool that does one wafer at a time (see What does a furnace do in a chip fab?).

Step 6: Contacts, covering with insulator, opening small holes, filling with metal

• What: Cover the wafer with a thick insulating layer and polish it flat, print tiny holes and etch down to the source, drain and gate: these are the contacts. Lay down a very thin barrier layer, fill the holes with a metal such as tungsten, and polish off what's left outside.
• Why: The wiring above may touch the transistors only at the points where it should; everywhere else has to stay insulated.
• Otherwise: A hole that doesn't reach the bottom or isn't filled has high resistance or doesn't conduct at all; a hole out of line that touches the gate makes a short. That is why every layer has to line up with the one below (overlay).
• Areas: Thin film, CMP, litho, etch, wet clean.

Step 7: The first metal layer, connecting the contacts into a circuit

• What: Cover with another insulating layer, dig trenches in the shape of the wires, fill them with metal and polish flat.
• Why: Only when wires connect the contacts do the two kinds of switch work as a pair, and does a group of switches become a circuit that can compute.
• Otherwise: However good the transistors are, unconnected they are just separate switches. For the layers of wiring stacked above, see How are a chip's wires made?
• Areas: Thin film, litho, etch, CMP, wet clean.

Where do the front end and the back end divide?

In a fab, this road is often split in two: steps 1 to 5, which build the transistors in the silicon, are front-end-of-line processing (FEOL), and from step 7 on, building the metal wiring above, is back-end-of-line processing (BEOL). The contacts in step 6 sit right on the line: some count them as front end, some as back end, and some call them the "middle of line". Some front-end steps run at over a thousand degrees Celsius, and once metal is on the wafer it can't be heated like that again, which is one reason for the split.

When people talk about the whole industry, "front end" means the wafer fab and "back end" means packaging and test (see How are computer chips made?). When you see "back end", check the context first.

Are today's transistors made this way too?

Same idea, different shape. In the most advanced chips, the channel mostly stands up as a thin fin, or is made of a few stacked sheets with the gate surrounding them on all four sides, and the gate and its insulating layer are made of other materials (see What is a transistor?). There are more steps and some come in a different order, but the main line is still there: keep them apart, make the bases, make the gate, make the entrance and the exit against the gate, then connect the wiring.

In fab24hr

In fab24hr's main story, The life of a chip, chapter 2, "Station by Station", is steps 1 and 2 of this article. In the first five days after wafer start, you are the R&D integration engineer, following the first 12 wafers of Glowmere, a fictional hearing-aid chip, along the R&D line: clean, grow the thin cushion oxide in the furnace, measure the monitor wafers, grow silicon nitride, print the first pattern, etch the trenches, polish down to the nitride with CMP (a little more as the recipe says, or stop the moment it touches), strip the nitride, and implant the n-type and p-type wells, doing one step by hand in each of the seven process areas.

The later steps are in A day in the fab: tap "Clock in", choose "A day in the fab", then on the "Your role today" card tap "R&D line", swipe to the R&D process engineer, and tap an area. The furnace engineer sets the oxide under the gate and the anneal, the implant engineer the source and drain, and the litho, etch, thin film and CMP engineers make the contacts together. The companies, chip, people, tools and figures in the game are fictional; each step follows public, general sources and is simplified. For other jargon, see Chip fab jargon in plain English.