How is the wiring inside a chip made? Vias, copper, and why the trenches come first

The wiring inside a chip, the interconnect, is built layer by layer on top of the transistors. First an insulating layer goes down. Trenches for the wires and small holes that reach down are dug into it, filled with metal (mostly copper today), and the surface is polished flat. Then the next layer goes on top. The most advanced chips stack more than ten layers of wiring. Fabs often call the transistor-making part the "front end of line" (FEOL) and the wiring part the "back end of line" (BEOL).

This "back end" is fab talk. When the industry says the back end is test and assembly, it means cutting the chips apart and packaging them (see "What is chip packaging?"), which is something else.

Why does a chip need so many layers of wiring?

At the very bottom of a chip are its transistors (billions of them in a big chip), made in the silicon: tiny switches controlled by electricity (see "What is a transistor?"). The result from each switch is the voltage on a wire, high or low (high is 1, low is 0), and it has to reach other switches. There are far too many wires for one layer, so a chip is built like an office tower: the ground floor is packed with switches, and every floor above it is corridors.

• Wires: metal lines running sideways within one layer, like the corridors on one floor.
• Vias: tiny vertical holes connecting the wires of one layer to the layer below, like stairways.
• Contacts: the holes at the very bottom, running from the first layer of wiring down to the transistors.

The contacts, closest to the switches, are often filled with a metal such as tungsten rather than copper, for a reason explained below. How transistors and contacts are made is in "How is a transistor made?"; this article covers the dozen or so layers above them.

How is one layer of wiring made?

Each layer of wiring goes through roughly the same six steps.

Step 1: Lay down an insulating layer

A thin insulating film, such as silicon dioxide, is laid over the layer below (see "What is thin film deposition?"). The wires are buried in this insulator so that they don't conduct into each other. Without it, two wires that should stay apart would touch and short out.

Step 2: Print the pattern, dig the trenches and holes

First, litho prints the shape of this layer's wiring onto photoresist, then etch digs shallow trenches and deeper small holes into the insulator. The trenches will hold the wires; the holes become vias that reach down to the wires of the layer below. Often the trenches and holes are dug one after the other in the same layer and then filled in one go, which is called dual damascene. If a hole isn't etched all the way down, the layers don't connect; if it goes too far, it damages the layer underneath. There are a huge number of holes, so fabs chain thousands together and measure them in one go (see "What is WAT?").

Step 3: Line them with a very thin barrier layer

Before any copper goes in, a very thin metal film called the barrier layer, often tantalum and tantalum nitride, goes onto the bottoms and walls of the trenches and holes. That's because copper atoms wander. If they get into the insulator, it stops insulating as well. If they reach the silicon below, they form "traps" inside it that make transistors leak. The barrier keeps the copper in, and also helps it stick. Without it, transistors slowly get worse, and it may not show right away.

After the barrier comes a very thin layer of copper, the "seed" for the next step.

Step 4: Electroplate, filling everything with copper

The wafer goes into a copper plating bath with a current switched on, and copper grows from the seed layer until it fills the trenches and holes. Additives in the bath make the bottom of a hole grow faster than its mouth, so it fills from the bottom up. The holes are narrow and deep: if the mouth closes over first, a gap is left inside, the current has trouble getting through, and in bad cases the connection breaks.

Step 5: Polish off the excess

The copper also covers the surface outside the trenches, joining every wire into one sheet. So CMP (chemical mechanical polishing) removes the copper and barrier outside the trenches, stopping when the insulator shows through, so copper stays only in the trenches and holes. A flat surface also lets the next litho step print sharply. Too little polishing leaves a bit of copper between two wires, and they short; too much makes the wires thinner and raises their resistance (see "What is CMP?").

Step 6: Seal the top, then build the next layer

A very thin protective film goes over the polished copper. The barrier only wraps the bottom and sides of the copper, so the top has to be sealed too, or copper would work its way up into the insulator of the layer above. Then it's back to step 1, once for every layer. The topmost layer is made into large metal pads that connect the chip to the outside (see "What is wire bonding?").

Why does copper have to be "dug first, filled after"?

Until about the late 1990s, wiring was mostly aluminum, made the opposite way: cover the whole wafer with aluminum, print the pattern, dry etch away the aluminum you don't want, then fill the gaps between the wires with insulator.

The switch to copper came because, at the same size, copper has only a little over 60% of aluminum's resistance. And when a lot of current flows, electrons keep bumping metal atoms along until, over the years, the wire thins and breaks; copper holds up to this better than aluminum.

The problem is that copper is hard to dry etch into lines. Dry etching relies on very reactive fragments in a plasma reacting with the surface and turning into a gas that is pumped away (see "What is etching?"). Copper's reaction products don't easily become a gas at temperatures the chip can take; they stay stuck on the surface, and the etch doesn't come out clean.

So it's done the other way round: if you can't etch the copper, etch the insulator, then fill in the copper and polish off the excess. This is called damascene, after an old metalworking craft of carving a pattern into a metal object and inlaying gold or silver into it.

Why are the bottom layers fine and the top layers thick?

The bottom layers connect neighboring switches: short distances, a huge number of wires, so they are the finest and densest. In the most advanced chips, the tightest wires sit only a few tens of nanometers apart (see The news says "2 nm").

The upper layers carry signals to the far side of the chip and deliver power to every switch. Long distances and large currents mean wide, thick wires, because a longer wire has more resistance and a thicker one less. Think of a city: the lanes outside people's front doors are narrow and many, and the highways across town are wide and few.

Why are copper-touched tools and wafers kept apart from the front end?

Even a little copper in silicon makes transistors leak. Front-end wafers still have very hot steps ahead of them (see "What does a furnace do in a chip fab?"). If one passes through a tool or a box that has touched copper and picks up a trace of it, the heat drives the copper into the silicon; the whole furnace load can be affected, and the furnace gets contaminated too.

So many fabs draw a line. Copper steps are done in a separate area or on dedicated tools. Wafers that have had copper don't go back to front-end tools. Wafer boxes and handling equipment stay on the copper side too. Copper on the back and edge of a wafer is cleaned off separately, so it isn't carried over when the wafer passes through measurement tools both sides share.

Why is wiring slowing chips down more and more?

A signal on a wire faces two hurdles. First, the thinner the wire, the higher its resistance. Second, two wires with insulator between them act like a small capacitor: the closer they are, the more a change of voltage on one tugs at its neighbor, and the slower the voltage can change.

Making transistors smaller usually makes them faster, but making wires thinner makes them slower. Below a certain size, copper's resistance climbs even higher than simple scaling predicts: electrons bump more often into the wire's surface and into the boundaries between the tiny crystals inside the copper, and the barrier can't keep getting thinner. So the more advanced the chip, the more of a signal's delay comes from the wiring, and the longer the wire, the more it shows. One answer is insulators that let neighboring wires disturb each other less (low-k dielectrics); engineers are also trying other metals for the finest layers.

In fab24hr

In fab24hr, several roles on the R&D line meet the same layer: a new contact. Tap "Clock in", choose "A day in the fab", then on the "Your role today" card tap "R&D line", swipe to the R&D process engineer and tap "Thin film" under the name: you're the thin film R&D process engineer (marked Beta). In the morning shift, the new holes are narrower, and you decide how thick the barrier layer should be. In the late-night shift, a cross-section photo shows a void under a contact at the wafer edge. In the afternoon shift of the R&D line's wet clean area, another group wants to run a lot with metal exposed at the wafer edge through the only cleaning tool: metal soaked in the bath stays on the tank walls, and every later lot in the same bath could pick it up.

Chapter 2 of the main story, The life of a chip, "Station by Station", digs the trenches at the very bottom that isolate the transistors: dig, fill with oxide, polish flat. It's the same rhythm as this article, except what goes in is an insulator. The game has no copper plating tool, and it doesn't say which metal fills the contacts. The companies, people, tools and figures are fictional; how chip wiring is made follows public, general sources. For other jargon, see Chip fab jargon in plain English.