What does a process integration engineer (PIE) do, and how is it different from a process engineer?

A process integration engineer (PIE, often just "Integration" for short) owns whether the chip is right once the whole process is done. A wafer goes through several hundred steps. Each process engineer looks after a few of them in one area. The integration engineer looks at all of them as one chain: what order they go in, which change in one step affects which later step, and whether the final electrical results and yield are right. When something goes wrong, they work back to find which step it was.

How is a process engineer different from an integration engineer?

A fab splits its hundreds of steps among a few areas: litho prints the pattern, etch cuts it, thin film adds a layer, and so on (see What do the seven process areas of a chip fab do?). Each area's process engineer looks after their own few steps and the group of tools that run them: is the film thick enough, is the line thin enough, are the numbers inside spec. For how they split the work with equipment engineers, read What's the difference between a process engineer and an equipment engineer?.

An integration engineer doesn't have an area. They have a product, or a whole process. The question isn't "did this step come out right?" but "now that every step is done, does the chip work?"

	Process engineer	Process integration engineer
Looks after	A few steps in one area, a group of tools	One product or one process, from the first step to the last
Mainly watches	That step's measurements and control charts	Every step's measurements, plus the electrical results and yield at the end
When something goes wrong	Checks their own step and tools	Works back from the result to the step and the tool

If every step is in spec, how can the chip still be wrong?

Because steps affect each other. Think of building a house. The plumber, the mason and the painter each follow the drawings. But if the hole left in the wall doesn't line up with the pipe, nobody can live there. Someone has to look at the whole house.

The same thing happens in a fab. The film from the thin-film step comes out a little thicker than usual, still inside spec. The etch step runs for its usual time, also inside spec. Put together, some of the tiny holes don't quite get etched all the way down, and the resistance of the contact between the transistor and the wiring above it goes up. Each step looks fine on its own. The problem is where they join.

Why can't the hundreds of steps go in any order?

An integration engineer has to know how each step relates to the ones before and after it. For example:

• Metal doesn't like heat: steps that need very high temperatures mostly come before the metal wiring is made. Once the wiring is in, the temperature has to stay lower.
• Heat adds up: every high-temperature step later on lets the atoms put into the silicon earlier move a little further. So the conditions of an early step have to allow for all the heat that comes after it. This is the thermal budget.
• Polish first, then print: if the surface isn't flat, the next litho layer won't print sharply, so the wafer is polished flat with CMP before each new layer of wiring.

In production, this list of steps is locked. It's called the POR (process of record). Changing any step goes through a change procedure, and "if we change this step, will anything later break?" is often the question the integration engineer has to answer.

What do integration engineers look at every day?

• Each step's measurements: film thickness, line width and so on, plotted on control charts. They tell you about that one step. They can't yet tell you whether the chip will work.
• The electrical test: when a wafer is finished, before it leaves the fab, probes measure test keys, small structures made just for measuring (mostly placed between the chips): the voltage at which a transistor starts to conduct, how much resistance, how much leakage. This is WAT. It measures electricity, not just sizes and thicknesses.
• Yield and wafer maps: later there is usually wafer sort, which tests every chip once. The share that comes out good is the yield (see What does "yield" mean in chip news?). Plotted by position, the results make a wafer map, and the shape the bad chips form is often a clue. For how WAT and wafer sort differ, read How are chips tested?.

When something goes wrong, how do they trace it back?

WAT and wafer sort can only be done once the whole wafer is finished, often weeks after the wafer start. At that point the integration engineer works like a detective, going back from the result:

1. Look at the shape first: bad chips scattered with no pattern look more like randomly falling particles. A ring around the edge, or a failure in the same place in every exposure field, usually has a specific cause.
2. Then look for what they share: the MES records which tool each lot went through, on which day, with which recipe. Compare the bad lots with the good ones and find the tool or step that only the bad ones went through.
3. Look upstream: put the measurements from several steps side by side and see which number started to move first. The electrical results are measured last; the first thing that moved is often much earlier.
4. Hand it to that step: once the most likely step is found, check it together with that step's process and equipment engineers. If needed, a wafer is cut open as a cross-section to look at the layers.

While the cause is being found, the lots still on the line that might be affected have to be put on hold or allowed to continue, and Integration often makes that call together with the process engineer.

When are they busiest?

With new products and new processes. The first few lots of a new product are its pilot run, and many problems are only found then. The integration engineer plans split lots: one lot of wafers is split into a few groups, each group changes just one condition, and one group changes nothing so there is something to compare against. When the results come back, they decide what the next lot should do.

A new process is often made stable on the R&D line first and then handed over as a whole to the production fab. Before it goes, it has to pass a transfer review: conditions, documents, reliability, checked one by one.

Who do integration engineers work with?

• Process engineers in each area: finding causes and changing conditions both depend on them.
• Equipment engineers: the tools' records and condition.
• Yield and product engineers: test data, and where the yield is being lost. Elsewhere, PE often means product engineer; see Is a PE a process engineer or a product engineer?.
• Manufacturing: where the lots are, and when hot lots need to ship.
• The customer's engineers: at a fab that makes chips for other companies, the customer asks "what happened to this lot, and when will we know?" Turning data into words the other side understands is sometimes Integration's job too.

Does every company split the work this way?

Not always. Job titles and the split of work differ between companies. Some split the work above among several groups; others leave more of it to one group. The title isn't always PIE either. What's above is a common way of splitting it.

The job means understanding how a transistor works and what each area does. People who like seeing the whole picture, piecing a cause together from data, and talking with a lot of different people tend to suit Integration.

In fab24hr

In fab24hr, tap "Clock in", choose "A day in the fab", then on the "Your role today" card tap "Production fab" and swipe to the process integration engineer. In the game this role is the "owner of the lot". Late at night, the first electrical results for a new product's first lot come in, a ring around the edge of the wafer map sits close to the spec limit, and the lot is due to ship to the test-and-assembly house at eight. In the morning, the hot lot H-2417 is on hold and the reason field is empty. In the afternoon, you write the instruction for a rework etch. In the evening, the customer, Leo, is on the line waiting for three plain sentences, and another product's contact resistance has crept up for two weeks; trace it upstream and the first thing that moved is the thin-film thickness. When you play the process engineer, Ya-Ting, the owner of H-2417, is the integration engineer.

In chapters 1–4 of the main story, The life of a chip, you are the R&D integration engineer on the R&D line: how to split 12 wafers, following them through the seven areas, the WAT and three wafer maps, and the night before the transfer review when the customer wants to start two weeks early. The companies, products, people, lot numbers and tools in the game are fictional; what an integration engineer does comes from public, general sources, and the actual split of work differs between companies.