What is shallow trench isolation (STI)? How transistors are kept apart

Shallow trench isolation (STI) means digging a shallow trench between every pair of neighboring transistors on the wafer surface and filling it with an oxide that doesn't conduct, so the transistors are kept apart from each other. It is one kind of device isolation, and it is the first step in building transistors on silicon: first you fence in where each one will go, and only then can the later steps go in.

This article takes step 1 of How is a transistor made? and opens it up.

Why do transistors need to be kept apart?

The transistors on a chip sit right next to each other. Each one is a small switch controlled by electricity (see What is a transistor?), and they are all made in the same piece of silicon. Silicon is a semiconductor, so it isn't a perfect insulator (see What is a semiconductor?). With nothing in between, current can slip through the silicon alongside and reach the next transistor.

The result is that neighboring transistors leak into each other and interfere with each other, and a switch that should be off doesn't turn off cleanly. This is one kind of leakage; for why leakage keeps a chip using power, see Why do chips use power?

So the small patch of silicon each transistor sits on needs an insulating wall all around it. The patch kept for the transistor is called the "active area", and the wall around it is the isolation.

How were they kept apart before? LOCOS and the "bird's beak"

The common method used to be local oxidation of silicon (LOCOS): cover the places to keep with silicon nitride, put the wafer in a furnace, and turn the exposed silicon directly into a thick layer of oxide that serves as the wall (for what thermal oxidation is, see What does a furnace do in a chip fab?). But oxygen creeps sideways under the edge of the nitride, so the edge of the wall grows into a pointed sliver, like a bird's beak, that reaches into the space meant for the transistor next to it. The bird's beak is hard to shrink along with the transistors, so the smaller they get, the bigger the share it takes up, and the surface isn't flat either. That is why the industry switched to digging trenches and filling them with oxide.

How is shallow trench isolation done? Step by step

Below is the order commonly found in textbooks and university course notes, simplified; a real flow also has several cleans and measurements in between.

Step 1: Grow a pad oxide, then lay down silicon nitride

• What: After the wafer is cleaned, it goes into the furnace, where a very thin layer of oxide, the "pad oxide", grows on the silicon surface. Then a thin-film tool lays down a hard layer of silicon nitride.
• Why: The nitride is the armor for this whole stage: it covers the places that aren't dug during the etch, and it is the layer where polishing stops. The pad oxide sits in between as a cushion, because nitride laid directly on silicon strains it and damages it.
• Otherwise: Without the nitride, neither the etch nor the polishing has anything to block it or stop it. Without the pad oxide, the silicon surface is left with defects, and that surface is exactly where the transistors will be made.

Step 2: Lithography, printing where to keep and where to dig

• What: In litho, coat the wafer with photoresist, expose it through a photomask and develop it, so the shape of the active areas is printed in the resist: covered areas stay for transistors, exposed areas will be dug into trenches.
• Why: This is the very first pattern on the chip, so there is nothing underneath to align with yet; from this layer on, later layers have something to align with (overlay).
• Otherwise: A pattern printed out of line or blurred gets the size and position of the active areas wrong. Luckily, resist that was printed badly can still be washed off and printed again (see What is photolithography?).

Step 3: Etch, digging the shallow trenches

• What: Plasma etches down along the resist pattern: first through the nitride and the pad oxide, then into the silicon, digging the trenches (see What is etching?).
• Why: The trench is the mold for the wall; whatever shape it is dug in, the wall takes. The sidewalls are usually given a slight slant on purpose, which makes the trenches easier to fill later, and the corners can't be too sharp either.
• Otherwise: If the depth varies, the wall is higher in some places and lower in others, and where lines are packed close together the etch often goes slower and the trenches come out shallower. So a test wafer that ran alongside is cut open to check the shape of the trenches.

Step 4: Grow a thin oxide on the trench walls, to repair them and round the corners

• What: Strip the resist, clean, and go back into the furnace, so that the silicon exposed on the walls and bottom of the trenches grows a very thin layer of oxide, called the "liner".
• Why: Silicon that has just been hit by plasma is damaged at the surface, and growing a layer of oxide repairs it and leaves a clean boundary between silicon and oxide. The sharp corner at the top of the trench also comes out a little rounder after the oxidation.
• Otherwise: Damage left behind leaks. At a sharp corner the electric field is concentrated, and the gate's insulating layer grown over it later also tends to come out thinner, so the transistor leaks more easily at its edge.

Step 5: Fill the trenches with oxide

• What: Fill the trenches with silicon dioxide by chemical vapor deposition (CVD), deliberately growing it thicker than the trenches are deep, so it covers the whole wafer (see What is thin film deposition?).
• Why: A trench has to be packed with insulator from bottom to top for the wall to be complete; the extra layer on top is left for the next step to polish off.
• Otherwise: If the top of a trench closes up first, a hollow, a void, is left inside, which is a hole in the wall. The narrower and deeper the trench, the harder it is to fill.

Step 6: CMP, polishing flat and stopping at the nitride

• What: CMP polishes off the extra oxide outside the trenches and stops once the nitride shows through. Nitride is harder to polish than oxide, so when the pad reaches it, the polishing force and the reflected light change, and that tells the tool it has arrived (see What is endpoint detection?).
• Why: The surface has to be flat for the next layer to print sharply, and the top of the nitride has to be clear for the next step to strip it.
• Otherwise: Polish too little and a thin layer of oxide still covers the nitride, so the next step can't strip it cleanly. Polish too much and the wide trenches sink in the middle like a shallow dish, which is called dishing. So the tool often polishes a little more as set, and the choice is a trade-off between the two (see What is CMP?).

Step 7: Strip the nitride and the pad oxide

• What: Soak the wafer in heated phosphoric acid (hot phosphoric acid), which dissolves silicon nitride but barely touches oxide; then dip it in dilute hydrofluoric acid to take off the pad oxide.
• Why: The nitride and the pad oxide are only tools for this stage. Once they've done their job they come off, leaving clean silicon for the transistors.
• Otherwise: Where nitride is left behind, the transistor there won't come out right. The hydrofluoric acid also eats a little of the oxide in the trenches, and after too many dips the wall ends up lower than the silicon surface, so how much each dip will take is worked out in advance.

What does it look like when it's done, and what comes next?

After the strip, the silicon surface is a set of islands. Each island is an active area, surrounded by trenches full of oxide, and the whole surface is roughly flat.

Only then are atoms implanted into the islands to make the wells, then the gate, the source and the drain, and finally the wiring. The first panel of the figure below is the isolation this article covers.

In fab24hr

In the main story, The life of a chip, chapter 2, "Station by Station", is mostly shallow trench isolation. In the first five days after wafer start, you are the R&D integration engineer, following the first 12 wafers of Glowmere, a fictional hearing-aid chip, along the R&D line: clean, grow the pad oxide in the furnace, measure the monitor wafers, grow the silicon nitride, print the first pattern and etch the trenches. On day 4, at CMP-R1, you watch the polishing table's force to find the endpoint.

Once it reaches the nitride, you choose: follow the recipe and polish a little more, and the wide trenches sink in a little; or stop the moment it touches, and on day 5, when hot phosphoric acid strips the nitride, a few spots won't come off, so the wafers get a dip in dilute HF and a second strip. After the nitride strip come the wells.

The game fits this stage into five days, covers the clean, the liner and the trench fill after the etch in narration, and doesn't show the pad oxide strip. The companies, chip, people, tools and figures in the game are fictional; each step follows public, general sources and is simplified. For other jargon, see Chip fab jargon in plain English.