What is overlay? Why does each layer of a chip have to line up with the one below?

Overlay is how well the pattern on one layer of a chip lines up with the layer below it, and the distance it's off by is the overlay error. A chip is printed one layer at a time by litho, often a dozen to several dozen layers, and each new layer has to land exactly on top of the one below. When the layers line up, they connect. When they don't, things that should connect miss each other, and things that shouldn't touch end up touching.

Why does every layer have to line up?

Think of a color print made with several carved blocks: red, yellow and blue each get their own block and are printed one at a time. If one block sits a little crooked, the color runs over the lines. A chip is stacked up the same way, only stricter: a tiny hole in the upper layer has to land right on a contact point in the layer below.

How the pattern gets printed is covered in What is photolithography?. This article is only about lining the layers up.

How far off can a layer be?

Much less than the finest line in the circuit. A rule of thumb in one set of university lecture notes is one third to one fifth of the minimum line width. A public university thesis gives an example: in the generation with 0.18-micrometer lines, the allowed error was about 0.06 micrometers.

For the newest generations, the technology roadmap the industry draws up together sets the target at just 2 to 4 nanometers. A human hair is tens of thousands of nanometers thick, so that's more than ten thousand times thinner than a hair.

How is a layer aligned, measured and fixed?

Alignment and overlay aren't the same thing. Alignment is what happens before exposure; overlay is the result measured after. One is aiming, the other is checking where you hit.

Step 1: Before exposure, find the alignment marks

• What: The wafer goes into the scanner but isn't exposed yet. A sensor looks for alignment marks left on the wafer by earlier layers (tiny crosses or gratings, usually placed in the narrow strips between chips that get cut away at the end). It measures where several marks are, works out how far the whole wafer is shifted, how much it's rotated and whether it has grown a little, and then decides where to print each field.
• Why: The wafer never sits in exactly the same spot, and earlier steps may have distorted it slightly. One point isn't enough.
• If not: Expose without aligning, and the layer won't land on the one below. Every wafer will be off in a different way, too.

The first layer has nothing below it to line up with, so the wafer is just turned the right way using the small notch on its edge. From that layer on, the later layers have marks to align to.

Step 2: Expose, develop, and print the measurement marks too

• What: The scanner exposes field by field at the calculated positions, and then the wafer is developed. Along with the circuit, the photomask carries dedicated overlay marks, which get printed right next to the marks of the layer below: for example, a large square on the lower layer and a small square inside it on this one.
• Why: After develop, the marks of the two layers sit side by side, so there's something to compare.
• If not: You'd only find out the layers were off once the chips were finished and tested electrically, weeks later.

Step 3: After develop, measure how far off it is

• What: A metrology tool looks at the marks of the two layers with light and measures how far the small square is from the center, and in which direction. Not every wafer is measured: a few wafers per lot, a few fields per wafer, often one point at each of a field's four corners. For how metrology tools see, read How does a chip fab know each step went right?.
• Why: Only by putting many points together can you see what kind of error the whole wafer has.
• If not: An error nobody catches goes straight into etch.

Draw each point as an arrow, and the errors fall into a few kinds:

• Left-right (x) and up-down (y): every arrow points the same way and is about the same length, like a sticker put on a little off-center.
• Rotation: the arrows circle around the center and get longer the closer they are to the edge, like a sticker put on crooked.
• Magnification (scale): the arrows point outward from the center (or inward) and get longer the closer they are to the edge, as if the whole pattern had been stretched or shrunk a tiny bit.

The whole wafer can have these, and so can each exposure field. Take them all out, and the scattered bit that's left, which no correction can remove, is called the residual.

Step 4: Too far off? Redo it while it's still in resist

• What: If it's out of spec, the lot is put on hold and someone decides whether to rework it: strip off the whole layer of photoresist, then coat, expose and develop again.
• Why: After develop, the pattern exists only in the resist. The material underneath hasn't been touched.
• If not: Once the wafer goes through etch, the misplaced pattern is cut into the material for good. Rework has a cost too: an extra pass, one more round of processing, a few more hours. When the error is small, someone has to judge whether it's worth it.

Step 5: Hand the error to the scanner so the next lot starts corrected

• What: The measured error (how much x, y, rotation and magnification) goes back to the scanner, which nudges the next lot the opposite way. That's called a correction. The amount is often worked out by a system automatically; see What is APC?.
• Why: On the same tool and the same product, the error tends to repeat. What you measure on this lot can be fixed before the next one.
• If not: Every lot comes out off in the same way, and each one is only caught after it's measured, then reworked.

Why does a layer end up off?

• The scanner itself: how the wafer stage travels, tiny distortions in the lens. Every scanner has its own small habits.
• The wafer gets pulled out of shape: the high temperatures of earlier furnace steps and the films grown on top can bow the wafer a little and stretch or shrink it, and the marks shift with it.
• Heat: a 1°C temperature difference makes a 30-centimeter silicon wafer about 0.8 micrometers larger across, hundreds of times more than the newest generations allow.
• Worn marks: CMP or etch can leave a mark lopsided, so the sensor reads its position slightly wrong.
• The two layers were exposed on different scanners: the two tools' habits differ and don't cancel out. So the most critical layers are sometimes kept on one scanner. The cost: when that one is busy, the others can't take the lot even if they're idle.

What happens when a layer is off?

A small hole in the upper layer has to land on a contact point or a wire below. The lowest ones, which reach down to the transistors, are contacts; the ones between two layers of wiring are called vias.

• It misses: off target, the touching area shrinks and the resistance goes up. In bad cases, nothing connects.
• It touches what it shouldn't: shifted sideways, it touches a transistor's gate or the next wire over, and that's a short circuit.

How these holes are made: How is a transistor made? and How is the wiring inside a chip made?. A small error doesn't always show right away. Often it takes WAT measurements weeks later to know whether the circuits connect.

In fab24hr

Tap "Clock in", choose "A day in the fab", then on the "Your role today" card tap "Production fab", swipe to the process engineer and tap "Litho" under the name: you're the litho process engineer. In the morning, lot P-3A08's overlay is out of spec, and its next step is etch. At the metrology tool you read the overlay map: the grid lines are exposure fields, and the yellow arrows show which way and how far this layer is off from the one below. Try shift, rotation and scale corrections; with the right one, the arrows shrink to a little residual. Then you check the records: the layer below was exposed on a different scanner. Keep the most critical layers on one scanner, or add the difference between the two tools to the correction? Finally, Ya-Ting in Integration needs an answer: rework, or run as is.

In the same area, the litho equipment engineer's late-night shift has the scanner stop because it can't find the alignment marks. On the R&D line, the litho R&D process engineer's morning shift aligns the contact layer to the layer below for the first time: after measuring overlay, you pick which terms to correct. In the main story, The life of a chip, chapter 2 "Station by Station", the first pattern has nothing below it to align to, so the wafer is placed by its notch. The company, people, lot numbers and figures in the game are fictional; how overlay is measured and corrected follows public, general sources. For other jargon, see Chip fab jargon in plain English.