What does an R&D integration engineer do with a new chip's first lot?

An R&D integration engineer is the person in charge of a new product on the R&D line: how to split the first wafers, whether the chips came out right, and when the product is ready for the production fab are all questions they have to answer. It is one kind of process integration engineer (PIE); job titles differ from company to company, and in English it is often called an R&D process integration engineer. The integration engineers in a production fab look after the lots made there in volume (see What does a process integration engineer (PIE) do?). The R&D side looks after the first few lots of a new chip, the very first time it is made.

How is R&D integration different from integration in a production fab?

The biggest difference: on the R&D side, everything is being done for the first time. The R&D line is where new processes and new products are made first. It has every kind of tool, but not many of each; it runs only a few wafers at a time, and conditions can change a lot. A production fab wants the same thing, made in volume, over and over.

Think of a restaurant working on a new dish. The R&D line is the test kitchen: one or two plates at a time, a little more salt, a little less heat, until it's right. The production fab is the central kitchen, following a fixed recipe and turning out the same taste every day. The R&D integration engineer is the one who takes the new dish from the test kitchen onto the menu.

The first few lots of a new product are called a pilot run. For more on how the R&D line and a production fab differ, read How is an R&D line different from a production fab?

The first lot has only a few wafers. Why split it?

Because the first lot has many questions to answer and not many wafers. A common approach is a split lot: divide one lot of wafers into groups, change one condition in each group and keep everything else the same, and leave one group with nothing changed as the baseline. Compare them at the end, and you can see what that condition did.

Like baking cookies: put one batch of dough on three trays, bake one two minutes longer, one two minutes shorter and one by the recipe. Compare them, and you know what the baking time does.

With so few wafers, every one counts:

• Put just one wafer in a group, and if something happens to it, you can't tell whether it was the condition or just bad luck.
• Someone wants a wafer to run ahead and try the new step first; someone else wants one for a cross-section, to look inside. A wafer that has been cut open can't be used again.
• When there are many conditions, changing one at a time is too slow. A statistical method called design of experiments arranges several changes together, so fewer wafers can show the effect of each one.

So the split plan often takes a meeting to settle, and the person in charge decides who gets a wafer and which group goes without.

What is a "corner," and why make wafers off-center on purpose?

The same design never comes out of the fab exactly the same: some transistors are a little faster, some a little slower. Designers need to know whether the chip still works at the far ends. So when the lot is split, a few wafers are made off-center on purpose, and these ways of being off are called corners.

A chip has two kinds of transistor, N-type and P-type. The middle is called TT. Both fast is FF, both slow is SS, and one fast, one slow is SF or FS. When both shift the same way, it mostly changes how fast the chip runs. One fast and one slow is trickier: the two kinds of transistor fall out of step, and some circuits may simply give wrong results.

It's like building a chair: the lightest and the heaviest people have to sit in it, not just someone of average weight. Which corner matters most depends on the product. A product that has to last a long time on a small battery fears leakage in standby most, and fast transistors leak the most, so the FF corner can't be skipped.

When the wafers are done, what do you look at first?

Most electrical results only come once the whole wafer is finished, often weeks after the wafer start. When they come back, two things come first:

• WAT: probes measure small structures left on the wafer just for testing, called test keys; most sit in the scribe lines between the chips. They measure the voltage at which a transistor starts to turn on, how big a resistance is and how much current leaks. This is WAT, and it is often one of the first places a whole lot shows up as off.
• Wafer maps: next, wafer sort tests every single chip, and the results are drawn by position as a wafer map. The shape the bad chips make is often the clue. A ring around the edge means finding out how the edge was made differently from the center. Bad chips in the same spot of every exposure field often follow the photomask. An arc is often left by a scratch. Bad chips scattered with no pattern look more like randomly falling particles. For how WAT differs from wafer sort, read How are chips tested?

One habit matters a lot: suspect the measurement first, then the process. If the tips of the probe card are dirty, the numbers drift too, and it looks just like a process problem.

The R&D side has one more job: every problem found has to become a condition for the next lot. Which group to run again, whether the next mask set should leave room for more test keys: these are often decided now, because once the masks are made, they are hard to change.

What has to be checked before the handover to the production fab?

Once the new process is stable and the new product's yield reaches its target, the whole package goes to the production fab. First comes a transfer review: conditions, tool settings, work instructions, training and reliability, checked one by one.

It's like the walk-through before handing over the keys to a house: how many keys, the meter readings, what still needs fixing, all written down. Anything marked "done" on the checklist needs something to show for it; anything not done needs to say how far there is to go. Common items:

1. The standard process: which kind of tool and which conditions every step uses, written up as the version production follows, called the POR. Once it is locked, changing any number goes through a formal change process, and there are public industry standards for how suppliers tell customers about process changes.
2. Work instructions and training: the people following them in the production fab may never have come to the R&D line to learn, so every step has to be written so that someone else can follow it.
3. Reliability: one common test is HTOL. Chips run nonstop for 1000 hours, about six weeks, under heat and voltage, to see whether any fail early. A common standard is three lots of 77 chips each, with not a single failure.

If reliability testing isn't finished but the customer is in a hurry, the question becomes whether to do a risk start: start lots in the production fab early. If they pass, the customer gets chips sooner; if not, those lots may be scrapped whole (see What is a wafer start?). The R&D integration engineer often has to lay out the cost on both sides and then give their own recommendation.

Does every company split the work this way?

Not necessarily. Job titles and the split of work differ between companies. Some have separate integration engineers for R&D and for production; at others the same group takes a product from start to finish. The job may also be called technology development or new product introduction. What's above is the common pattern.

In fab24hr

In fab24hr, tap "Clock in", choose "A day in the fab", then on the "Your role today" card tap "R&D line" and swipe to the R&D integration engineer. The four shifts are different days in the life of "Glowmere", the customer's hearing-aid chip. The morning shift is the day before wafer start: in the split meeting, three people want some of the 12 wafers, and you split them. The late-night shift is day six after wafer start: the 12 wafers have just been cleaned, the furnace for the next step has stopped, and there are 90 minutes of Q-time left. The afternoon shift is a month or two later: one WAT item fails, there are three wafer maps, and you decide whether the next mask set keeps room for your own test keys. The evening shift is about four months later: the night before the transfer review, you go through the checklist, and the customer wants the chips two weeks early.

In the main story, The life of a chip, the R&D integration engineer is the lead in chapter 1, "How to Split 12", chapter 3, "The shape of a failure", and chapter 4, "Two Weeks Early". In chapter 2, "Station by Station", the same person follows those 12 wafers through the seven process areas. The companies, products, people, lot numbers, tools and figures in the game are fictional; what an R&D integration engineer does comes from public, general sources, and the actual split of work differs between companies.