How is an R&D line different from a production fab?
An R&D line (also called a pilot line) is where new processes and new products are made for the first time. A production fab is where things that already work are made every day, in volume, exactly the same each time. An R&D line runs a few wafers at a time and often splits a lot to try different conditions. Its question is "can we make it, and if it fails, why?" A production fab asks "is every wafer the same, and are we making enough, on time?"
What is an R&D line?
A wafer goes through several hundred steps before it becomes chips. That whole chain of steps, plus which tool and which settings each step uses, is called the "process" (for what each area does, see "What do the seven process areas of a chip fab do?").
With a new process generation, or a new product that changes a few steps, nobody knows what the new settings will do. Someone has to try them first, and that place is the R&D line. It has every kind of tool, so a wafer can go from the first step to the last. But it often has only one or two of each kind, with no spare if one breaks. A new product's first few lots, the pilot run, are often made here.
Every time transistors shrink by a generation, the new way of making them is worked out on an R&D line first (see "What is Moore's law?").
Why not just experiment in the production fab?
Because the production fab's tools are booked every day with lots that have to ship. One research paper looked at exactly this: when R&D lots run on a production line and get priority, the regular lots slow down, and the line finishes less each day. It works the other way too. R&D lots often get pushed behind the lots that have to ship, and the results take a long time to come back.
So many places keep a separate R&D line. Some share most of their tools between R&D and production instead. That saves money, but the two sides compete for the same tools. Public descriptions of pilot lines often use the phrase "low volume, high mix": only a little of each thing, but many different things.
What happens on an R&D line each day?
An R&D line is like a test kitchen working on a new dish. It cooks a few portions at a time, a little more salt in this one, a hotter flame in that one, and tastes every one.
- Lots are split: one lot of wafers is divided into groups. Each group changes just one condition, and one group changes nothing, so there's something to compare against. This is a split lot. Compare them at the end, and you know what that one condition does.
- Settings keep changing: the same tool may run one product's new temperature in the morning and another product's new material in the afternoon.
- Plenty of measuring: every group is measured, and wafers are often cut open to look at a cross-section under a microscope. Measuring this much is how you find out which step a difference came from.
- Only the steps you need: if only one part of the process is being tested, often only those steps are run, making special test structures. This is called a short loop. Fewer steps, faster results.
What an R&D line cares about most is how fast it learns. The sooner results come back, the sooner the next round can start. It also accepts far more variation than a production fab. A wafer that fails still teaches something: why it failed.
What does a production fab care about?
A production fab is like a central kitchen that turns out thousands of lunch boxes a day. Once the recipe is set, everyone follows it. Every box has to be the same, and even switching to a different soy sauce has to be tested first.
- Volume and repetition: a lot is often a full box of wafers, up to 25. Several tools take turns on the same step, so if one goes down, there are others.
- Different numbers matter: yield (what share of the chips come out good), capacity (how much can be finished each day), delivery (whether the customer gets it on time), and cost.
- Settings are locked: which kind of tool and which settings every step uses are written in a standard process called the POR. To change one number, you first have to show the change is safe, and sometimes the reliability tests have to be done again. A public industry standard also requires suppliers to tell customers in advance about a major change to a product or process.
| R&D line | Production fab | |
|---|---|---|
| How much at a time | A few wafers, often split into groups | Up to 25 wafers per box, many boxes a day |
| Tools of one kind | Often just one or two | Several, so one can stand in for another |
| Settings | Always changing; that's the point | Locked in the POR; changes need proof first |
| The usual question | Can we make it? Why did it fail? | Is every wafer the same? Enough, on time? |
How does a new process get to the production fab?
When the process is stable on the R&D line, yield has reached the target and the reliability tests have passed, the whole package goes to the production fab. This is technology transfer, or "tech transfer" for short. It's more than one list of settings. It usually includes:
- The standard process: the tools and settings for every step, written as the POR.
- Specs: what each step's measurement should be, and where the electrical results should land when the wafer is finished.
- Documents: work instructions that spell out, step by step, how to run the tools and change parts, so someone else can follow them and get the same result.
- Training: people from the production fab come to the R&D line first to learn how it's actually done.
- Reliability data: proof that the chips won't fail early, even after long use.
Before it goes, it has to pass the transfer review, item by item.
The hardest part is often the tools. Run the same settings on a different tool, and the result can change: how worn the parts are, what state the tool itself is in, every tool is a little different. A production fab has several tools of each kind, and each one has to be tuned to give the same result. This is called tool matching. One approach makes the production fab's tools and settings as close to the R&D line's as possible. Others hold that production doesn't have to copy every step, as long as what comes out is the same.
After the handoff, yield in early production usually still has some way to climb (see "What does "yield" mean in chip news?"). Sometimes the reliability tests haven't finished and the customer can't wait, so wafers are started in the production fab anyway. This is a risk start; see "What is a wafer start?".
What do people on an R&D line do?
- R&D process engineer: looks after one area, such as etch, litho or the furnace. The settings for a new step are worked out by them on that area's tools: try a few groups, measure, look at cross-sections, settle on one, and finally write it into that step's box in the POR.
- R&D integration engineer: looks after more than one area. They own the whole flow and a new product's first lots: how to split the experiments, and whether the result is ready for the production fab. See "What does an R&D integration engineer do?". For the person who owns the whole flow in a production fab, see "What does a process integration engineer (PIE) do?".
- An R&D line also has equipment engineers who look after the tools, and technicians.
Job titles and the split of work differ between companies; this is a common way to divide it.
In fab24hr
fab24hr's R&D line has 8 roles: the R&D integration engineer, plus an R&D process engineer for each of seven areas: litho, etch, thin film, CMP, furnace, implant and wet clean. Tap "Clock in", choose "A day in the fab", then on the "Your role today" card tap "R&D line" and swipe to the job; for an R&D process engineer, tap an area under the name. In the etch area's morning shift, only ETCH-R1 can run the new step, and it has just gone down. In the evening shift, the standard process goes to the production fab tomorrow, and the POR still has one last box for you to sign. In the furnace area's evening shift, the production fab's furnace has run the R&D line's settings: same numbers, but the thickness doesn't match. Chapters 1 to 5 of the main story, The life of a chip, are on the R&D line too: from the day before wafer start, deciding how to split the first 12 wafers, to the eight-item checklist on the night before the transfer review. The companies, products, people, tool IDs and schedules in the game are fictional; how an R&D line differs from a production fab and what a tech transfer hands over come from public, general sources, and real practice differs between companies. For other jargon, see Chip fab jargon in plain English.
Where you'll meet it in the gameIn A day in the fab, tap "R&D line" to play the R&D integration engineer or an R&D process engineer in one of seven areas. Chapters 1–5 of the main story, The life of a chip, are on the R&D line too; chapters 4 and 5 are the night before the transfer review.
In fab24hr, only one tool can run the new step. Once it's stable, you still have to fill in the last box of the POR before it goes to the production fab.
Play as the etch R&D process engineer on the R&D lineTeachers: this article can go with "fab24hr in the classroom" in class.
More articles
What does the customer liaison at a test-and-assembly house do?
What jobs are there in the semiconductor industry? From chip design to the fab to test
What's the difference between a process engineer and an equipment engineer?
Is a PE a process engineer or a product engineer?
- What is fab24hr?: the two ways to play, the four shifts, common questions, sources
- The life of a chip: the life of one chip: tape-out, pilot run, mass production, wafer test, packaging, shipping
- A day in the life of a fab engineer: who does what (PE, EE, PIE, manufacturing), and the day hour by hour
- Who works in a chip fab: technicians, Manufacturing, process, equipment, Facilities, integration, QA, production control, masks, R&D, the chief, the vendor, and test and assembly at the test-and-assembly house: each role's day
- Chip fab jargon in plain English: MO, Hold, Q-time, OCAP and the rest, one plain sentence each
- Chip fab machines, taken apart: What 25 chip fab machines do (etch, scanner, CMP, furnace, packaging…), each as a 3D model to take apart
- fab24hr in the classroom: Semiconductor lesson plans: 20/40-minute plans, a lesson per chapter or process area (3D machines, the game, articles), discussion questions, a worksheet, FAQ
- About and press kit: trailer, gameplay clips, descriptions and key facts