What is a TSV (through-silicon via), and how do stacked chips connect straight through?

TSV stands for through-silicon via: a very fine hole made all the way through a silicon chip and filled with metal, so signals and power go straight from one side of the chip to the other. With it, chips can be stacked on top of each other and connected right through the middle. Much of what the news calls 3D ICs or 3D packaging relies on it.

Where does a chip normally connect to the outside?

A chip is built on the front of a wafer. The circuits are on the front, and so are the small metal pads that carry power and signals in and out. The back is just plain silicon. There are two common ways to connect a chip to the outside. With wire bonding, the chip faces up and fine wires run out from pads around its four edges, one by one (see "What is wire bonding?"). With flip chip, the chip is turned over and the small bumps across its whole face are soldered down at once (see "What is flip chip?").

But both use only the front; the back has no way out. When several chips are stacked, signals from the upper layers usually have to get down by wires that run around the edges.

Why go straight through?

To stack chips with wire bonding, every layer's pads have to stick out at the edge, and wires run from each layer down to the board, so the paths are long. The pads can only sit along the four edges, so there aren't many of them.

A TSV goes straight down through the middle of the chip. The path is only as long as one chip is thick, and the holes don't have to crowd along the edges, so there can be far more connections. A shorter path means faster signals and less power.

The stacked memory next to AI chips has over a thousand data lines per stack, and these holes carry them down layer by layer (see The news says "HBM". What is it?). When chips sit side by side on an interposer, the interposer often has TSVs too, carrying signals down to the package board (see The news says "advanced packaging").

How narrow and how deep is a TSV?

General sources roughly agree: the hole is a few micrometers to a dozen or so micrometers wide (a micrometer is a thousandth of a millimeter), far thinner than a hair, and a few tens of micrometers to around a hundred micrometers deep. It is often about ten times deeper than it is wide, like a narrow, deep well dug into the ground.

How is a TSV made, step by step?

The holes can be made early or late; a common choice is after the transistors are built and before the wiring above them. In general terms, there are about five steps.

Step 1: Etch deep, narrow holes into the silicon

First, litho prints where the holes go, then plasma dry etch digs down, often by etching a little, coating the sidewalls with a protective film, etching a little more, and repeating many times (see "What is etching?"). That keeps the holes straight and deep without taking room from the circuits next to them; at this point the bottom of each hole is still buried in the silicon. If the etch ate sideways too, the walls would get hollowed out, the later films wouldn't coat them evenly, and the copper would be hard to fill in.

Step 2: Line the walls with an insulating layer and a barrier layer

First comes an insulating film on the walls (silicon dioxide, for example), then a very thin barrier layer (often a metal such as tantalum or titanium, or its nitride), and finally a very thin layer of copper as the "seed" for plating. Silicon conducts a little on its own, and copper atoms are good at wandering; once they get into silicon, they cause leakage in transistors (the barrier idea is explained in "How is the wiring inside a chip made?"). Without these two layers, signals leak into the silicon, and the transistors nearby slowly get worse.

Step 3: Fill the holes with copper by plating

The wafer goes into a plating bath with current running, and copper grows from the seed layer, filling each hole from the bottom up; the extra copper on the surface is removed by CMP, and then the wiring is built on top as usual. Copper conducts well, and growing it from the bottom up leaves no gaps inside. If the mouth of a hole closes first, a void is trapped inside, current flows poorly, and that spot is more likely to fail later when it heats up.

Step 4: Grind the wafer thin from the back until the holes show

The front of the wafer is first bonded to another wafer or a glass plate that holds it up. Then the back is ground down with a grinding wheel, and CMP and etching take off the rest bit by bit, until only a few tens of micrometers are left and the bottoms of the copper columns show (see "What is CMP?"). The wafer starts out a little under a millimeter thick while the holes are only tens of micrometers deep, so without thinning they'd never come through; silicon this thin can't hold itself up, so the back-side pads are made while it's still on the support, and only then is it released and diced. Grind too little and some holes don't show; grind too much or unevenly and the copper columns get damaged.

Step 5: Stack the layers and line them up

The chips are stacked layer by layer, with the copper columns showing on the back of each layer lined up with the pads of the next. A common way is to put a tiny bump on each pad (usually a copper pillar with a little solder on top) and join them with heat and pressure; these microbumps are a few tens of micrometers apart. Lined up, signals and power pass down layer by layer; off by a little, and a connection misses or touches the one next door.

What is hybrid bonding?

Another way to join the layers skips the bumps. It's called hybrid bonding:

1. Polish until extremely flat: the faces to be joined are polished by CMP until their height varies by less than a nanometer, only a few atoms high. The surface shows copper pads with the insulating layer around them, and the copper sits on purpose a tiny bit lower, just a few nanometers.
2. Press together at room temperature: after the surfaces are treated, they're lined up and pressed together, and the insulating layers grab onto each other and stick at room temperature.
3. Heat to connect: then the stack is heated to a few hundred degrees. Copper expands more with heat than the insulating layer, closes that tiny gap, and the copper pads fuse into one piece.

Copper to copper and insulator to insulator, joined at the same time: that's why it's "hybrid". With no solder balls, connections can be smaller and closer together, down to less than ten micrometers apart. Let's try made-up numbers: at 40 micrometers apart, one square millimeter fits 25 × 25 = 625 connections; at 10 micrometers apart, it's 100 × 100 = 10,000, sixteen times as many.

The price is that everything has to be extremely flat and extremely clean. One invisible particle caught in between, and a large area around it fails to bond; research estimates that the unbonded patch can be hundreds of times wider than the particle.

Small chips stacked together or placed side by side are often designed and made separately. To connect, both sides first need a common interface: an agreement on how the pads are laid out and how the signals are sent (see "What is a chiplet?").

Why are TSVs hard to make?

• The holes are hard to fill: they're deep and narrow, every film has to reach the bottom, and the copper has to grow from the bottom up; anywhere it's uneven, a void is left.
• Copper and silicon expand differently with heat: by general figures, copper expands about six to seven times as much as silicon for the same rise in temperature. Every time things heat up, the copper column pushes on the silicon around it, and may even be squeezed a little out of the mouth of the hole, pressing into the wiring above. Transistors nearby get pushed and behave a little differently, so a small ring around each hole is often kept free of transistors.
• The wafer has to be ground very thin: silicon only a few tens of micrometers thick bends and cracks easily, which makes lining up and joining harder. Backside power delivery also grinds the wafer from the back, only much thinner still.
• The more layers, the harder the testing: every layer is tested before it goes on the stack (wafer sort), but thinned wafers are fragile and have few pads a probe can touch; once stacked, the probes can't reach the layers in the middle at all. One bad layer and the whole stack is unusable.
• The heat can't get out: chips in the middle are covered above and below, so their heat has to pass through other chips to escape.

In fab24hr

There are no TSVs and no stacked chips in the game. The hearing-aid chip "Glowmere" in the main story, The life of a chip, goes into a small SiP module at a test-and-assembly house; the module holds just one chip, connected out from its edges by wire bonding.

The closest thing is the assembly line at the test-and-assembly house. Tap "Clock in", choose "A day in the fab", tap "Test-and-assembly house" on the "Your role today" card and swipe to the assembly process engineer, who looks after dicing, die attach, wire bonding and molding. The note at the dicing saw says the wafer is first ground thin from the back, then cut apart, though not to reveal any holes. The note at the wire bonder says one chip has a dozen or so wires: with that few connections, connecting from the edges is enough.

The flatness hybrid bonding needs also comes from CMP. On the same card, tap "R&D line", swipe to the R&D process engineer and tap "CMP" under the name: you're the CMP R&D process engineer (marked Beta). On the morning shift, the goal is to polish the metal in the new contacts so it ends up level with the insulating layer next to it.

The companies, chips, people and machines in the game are fictional. TSVs and hybrid bonding are described from public, general sources and don't represent any one company's approach, and the spacing used to count connections is made up. For other jargon, see Chip fab jargon in plain English.