What is backside power delivery? Why chips are moving their power lines to the back of the wafer

Backside power delivery (often shortened to BSPDN, for backside power delivery network) is a new way of building chips: the power lines that feed the transistors move from the front of the wafer to the back, and the front is left mostly for the wires that carry signals. Moved to the back, power can take wider, shorter paths, and the front gets room back. The price is that the wafer has to be flipped and thinned to almost nothing from the back, which makes the chip much harder to build. Only the most advanced generations have started to use it, and each maker does it a little differently; this article covers the general idea only, with numbers given as rough sizes.

How does power reach the transistors in today's chips?

Transistors are tiny switches controlled by electricity, built into the front surface of a piece of silicon (see "What is a transistor?"). Above the switches, layer after layer of metal wiring is stacked up, more than ten layers in the most advanced chips. It's like an office tower: the ground floor is packed with switches, and every floor above is corridors (see "How is the wiring inside a chip made?").

The wiring does two jobs:

• Carrying signals: sending the result of one switch on to other switches. The result is the voltage on a wire, high or low: high is 1, low is 0.
• Delivering power: every group of switches has to be connected to the power supply (the high-voltage line) and to ground (the low-voltage line), so it can connect its output to one or the other (see "What is CMOS?").

Both kinds of wire are crammed onto the front. Power comes in at the very top, the side that connects to the package (see "What is flip chip?"), and works its way down, layer by layer, to the finest layers at the bottom before it reaches the transistors.

What's wrong with keeping the power lines on the front?

1. The voltage drops all the way down

Wires have resistance: the thinner and longer the wire, the more resistance it has. When current flows through resistance, some voltage is lost, roughly current times resistance. This is called IR drop.

Think of water in a tall building. It flows down from a tank on the roof, and the thinner and longer the pipes, the weaker the flow at the last apartment. Electricity is the same: by the time it reaches a switch, the voltage is already a little lower than the supply.

With too little voltage, a switch flips more slowly. Lose too much, and a signal may not arrive before the next clock tick, so the chip can get an answer wrong. Chip designers often keep the allowed drop within about a tenth of the supply voltage. If that isn't enough, the supply voltage has to go up, and the chip uses more power.

2. The signal wires get squeezed

To lose less voltage, power lines have to be wide and many, and they take up a lot of room on every layer. The bottom layers are the most crowded to begin with, so signal wires have to take detours, or more layers have to be stacked on.

As switches get smaller and denser (see "What is Moore's law?"), wires get thinner and both problems get worse. So engineers asked: why not move the power lines to the other side, where they don't compete with signals?

How is backside power delivery made, step by step?

In general terms, there are about five steps.

Step 1: Build the transistors and signal wiring on the front as usual

The transistors and the wiring above them are built on the front just as today, except that the wiring is mostly left for signals. Some approaches also leave spots next to the transistors where the backside will connect later. The transistors come first because making them involves very hot steps that metal wiring can't survive (see "How is a transistor made?").

Step 2: Flip it over and bond it to a carrier wafer

The finished wafer is turned face down and bonded to another wafer, called a carrier wafer. The carrier has no circuits on it. It's there to hold things up. It's needed because the next step thins the original wafer until it can't support itself: without a carrier, the thinned silicon would break as soon as it was picked up, and nothing would protect the wiring on the front. The bonding uses techniques close to the ones for stacking chips (see The news says "advanced packaging").

Step 3: Thin the original wafer from the back

A wafer starts out less than a millimeter thick. Now almost all of its silicon is removed from the back: first a grinding wheel takes off most of it, then CMP and etch remove the rest a little at a time (see "What is CMP?"). What remains is around a micrometer thick, and in many approaches even less (a micrometer is a thousandth of a millimeter). Often a layer that is harder to remove is buried under the transistors beforehand, and the thinning stops when it reaches it.

It has to be this thin because the holes dug in the next step are only tens to hundreds of nanometers wide, and a hole that narrow can't go very deep. If the silicon isn't thin enough, the holes never reach the transistors. Wafers are thinned from the back before packaging too, often to about the thickness of a sheet of paper (see "What is chip packaging?"); here they go tens of times thinner or more. And the whole 30-centimeter wafer has to come out evenly thin: thin too far and the transistors are damaged, not far enough and the holes don't connect.

Step 4: Dig holes from the back to reach the transistors

On the thinned back, litho prints a pattern, etch digs very narrow holes, and metal is filled in, passing through the thin layer of silicon left to connect to the front. These holes through the silicon are the same idea as the through-silicon vias used to stack chips in advanced packaging, only much finer.

Most of the differences between approaches are in where the holes land. Some connect to the power lines in the lowest wiring layer on the front, some to a power line buried right next to the transistors, and some directly to one end of a transistor. The more direct, the shorter the path, and the harder it is to make.

The holes have to line up with tiny spots on the front. But during the bonding in step 2, the wafer gets stretched out of shape very slightly, which makes the pattern on the back harder to line up (this is called overlay; see "What is overlay?"). Off by a little, and a hole misses, or connects where it shouldn't.

Step 5: Lay wide, short power lines on the back

A few layers of metal lines just for power are stacked on the back, with contact points on the outside that connect to the package. With no signal wires competing for room, these lines can be wide and thick, so their resistance is low; if they were as thin as the ones on the front, moving them would be pointless. Power now enters from the package and reaches the transistors after only a few layers, and the dozen or so fine layers on the front no longer have to carry it.

What's better about moving power to the back?

• Less voltage is lost: power takes wider, shorter paths, so the switches get a steadier voltage.
• The front is freed up for signals: without the power lines, signal wires don't have to detour as much.
• Circuits can be packed tighter: every row of switches used to give up a track to a power line. With that gone, research estimates the same row of switches can take roughly 10 to 20 percent less area.

What's hard about it?

• Extreme thinning and alignment: the whole wafer has to be thinned to around a micrometer or less, evenly, and the holes on the back have to line up with spots on the front, making up for the slight stretching from bonding.
• Heat is harder to get out: transistors used to sit right against a thick block of silicon that carried their heat away. Now the power lines are on one side and the dozen or so wiring layers are on the other, so heat has to get through the insulation between wires, which doesn't conduct heat well.
• Faults are harder to find: to locate a fault, engineers often look at the transistors from the back, through the silicon, with infrared light (see "What is failure analysis (FA)?"). With the back covered in metal, they can't see in, and other methods are needed.
• More steps, more cost: bonding, thinning and the backside layers add steps, and any of them can go wrong and hurt yield.

That's why only the newest generations have started to use backside power delivery; a new technique usually takes many years to go from research to mass production (see "How long does a new chip technology take to go from a paper to mass production?"). Most chips today still have their power lines on the front: older generations have wiring that isn't as fine, and that works well enough (see The news says "mature nodes").

In fab24hr

The game doesn't show this part. No wafer gets flipped and bonded to a carrier, and there are no power lines on the back. Glowmere, the chip in the main story The life of a chip, is a hearing-aid chip made in a mature process generation, not one of the newest.

The closest place is the R&D line. Tap "Clock in", choose "A day in the fab", then on the "Your role today" card tap "R&D line", swipe to the R&D process engineer and tap "CMP" under the name: you're the CMP R&D process engineer (marked Beta). New contacts filled with metal have to be polished flat, and the whole R&D line has only one tool for it, CMP-R1. The contacts are the last stretch where the wiring connects down to the transistors. On the morning shift, the new contacts are laid out differently from the last product, but the recipe in hand was worked out for that product on blanket wafers: polish one wafer first, or all three together? At the test-and-assembly house, the dicing saw's card also says wafers are thinned from the back first, but that is thinning before packaging, and it leaves the wafer far thicker than backside power delivery does.

The companies, people, tools and numbers in the game are fictional. Backside power delivery is described from public, general sources and does not represent any one company's approach. For other jargon, see Chip fab jargon in plain English.