What is failure analysis (FA), and how do engineers find out why a chip failed?

Failure analysis (FA) means finding out, for one chip that has failed, exactly where it broke and how. It follows one rule: work from the outside in, and do the harmless things before the destructive ones. First power the chip up and look at it from the outside to narrow things down to one spot, and only then open that spot up. The evidence goes to the people who look for the root cause and work out how to stop it happening again.

What is failure analysis looking for?

A test only tells you "this chip failed". Every finished chip is powered up and tested (see How are chips tested?), but the tester usually knows only which item didn't pass. It doesn't know which of the chip's tens of millions to tens of billions of switches, or which spot in its many layers of wiring, actually went wrong.

Failure analysis answers the next question down: where is the damage? Is it a broken line, two lines touching, or a hole that never got filled? Once you can see what it really looks like, you know which step, and which tool, to go and check.

Where do the failed chips come from?

Mostly from three places:

• Inside the fab: a WAT item is out of spec, some chips fail wafer sort, or the yield drops (see What is WAT, and how does a wafer map show what went wrong?). An R&D line working on a new process often cuts open a wafer even when nothing has failed, to see whether what it built looks right.
• The test-and-assembly house: a chip fails final test, or fails early in a reliability test (see What is burn-in?).
• Returned by the customer: it failed after going into a product, and the customer opens a return form and sends it back.

How is it done? Outside in, one step at a time

It's like seeing a doctor: first they ask where it hurts, take your blood pressure and an X-ray, and surgery comes last. A chip is the same. Each step does more damage than the one before, and damage can't be undone.

Step 1: Reproduce the failure and measure it

Power the chip up and test it again under the conditions it failed in: which pin, how hot, how high the voltage, with a good chip alongside for comparison. This proves it really is bad, and shows how it's bad: a break (an open), two things touching (a short), or more leakage than there should be. Skip it, and you might take apart a chip that was never broken, only badly connected the first time, and destroy it for nothing.

Step 2: Look from the outside before opening anything

This step is often done together with step 1, and which comes first varies from place to place. An optical microscope checks the package for cracks, X-rays check whether the metal wires and solder joints inside are broken, and ultrasound checks whether the plastic has come away from the chip (sound bounces almost entirely off a gap, while a gap this thin often doesn't show up on an X-ray). None of these normally harms the chip, and package problems often show up right here. Open it first, and the cracks and gaps can get disturbed, so no one can say any more whether they were there before or came from opening it.

Step 3: Power it up and find the spot that heats up or glows

The chip is sealed in plastic where a camera can't see it, so a small opening is often first dissolved in the package with strong acid to expose the chip, leaving the fine wires inside in place so it still powers up. Then keep the chip powered under the conditions that make it fail, and photograph it with a very sensitive camera: a short or a leak often runs a little hotter than its surroundings, or gives off a very faint light. If the metal layers on top are in the way, look from the back: infrared light passes through silicon. A chip often has hundreds of millions of switches, and the next step can only cut into a tiny area, so you need to know where to cut. Cut without finding the spot first, and you'll almost never hit the one place that's broken.

Step 4: Dig down to that spot

The wiring on top of the chip is polished or etched away one layer at a time, stopping at the layer where the damage is. To look at just one spot, a focused ion beam (FIB) digs open only that tiny area with a very fine beam of ions. Defects are often buried under several layers of wiring, and you can't see them until you reach that layer. There's no going back after this step: dig in the wrong place, or polish too deep and take off the broken layer too, and the evidence is gone.

Step 5: Image the cross-section with an electron microscope and analyze it

The exposed cross-section is imaged with a scanning electron microscope (SEM); for finer detail, a very thin slice is cut and put in a transmission electron microscope (TEM). When electrons hit a material, each element also gives off its own X-rays, and measuring them tells you what that spot is made of. That's how you see whether a hole wasn't filled, a line broke, or an extra particle is sitting there. From the shape alone, you only know "something extra is here"; knowing what it's made of lets you guess which step, and which material, brought it in.

Step 6: Write the conclusion and pass it on to the people looking for the root cause

Write down where it broke, what the damage is, which methods were used, and which images are the evidence. Failure analysis answers "how did it break?"; why it happened and how to stop it happening again also takes the tool records and the steps each lot went through (see What is root cause analysis?). Write only "there's a void" (an empty pocket), and no one fixes the step that made it, so the next lot comes out the same.

Why not just cut every chip open?

Because cross-sectioning destroys that chip, or the whole wafer, and it takes a lot of time. So in normal running, a factory uses tests and inspection to find which chips and wafers have a problem (see What is wafer defect inspection?), sends only the most suspicious ones for failure analysis, and then cuts open only the most suspicious spot.

In fab24hr

In chapter 3 of the main story, The life of a chip, "The shape of a failure", you're the R&D line's R&D integration engineer. The WAT for the first lot of the new chip "Glowmere" is back: wafer 9's contact resistance is 30% over spec. Hsiao-Wen in the Electrical test lab asks you: probe it again, or write it into the report as a process problem? That's step 1: make sure it isn't a bad measurement. If you gave Zhou a wafer for cross-sectioning in chapter 1, he tells you that when they cut it open there were small voids under the contacts, only in a few chips at the edge. If you didn't, he says: "Without a cross-section, all we can do is guess from the electrical data."

In A day in the fab, on the "Your role today" card, tap "R&D line", swipe to the R&D process engineer, and tap "Etch" under the name (shifts follow the time on your device). On the late-night shift, the analysis lab's night shift sends you a cross-section image, and you tap the void at the bottom of a contact near the edge, where the metal never filled in. Zhou says that to be sure whether the etch or the metal fill caused it, they need TEM: their own machine is booked by another team today, so do you borrow four hours from them, or send it to an outside lab and wait two weeks?

Tap "Test-and-assembly house" and swipe to the customer liaison: on the morning shift, an engineering sample comes back because it won't power on once it's soldered to the board. Fang in the reliability lab says: "Go through them one by one, and don't jump to a conclusion." Once you've gone through the electrical test, the visual inspection, the X-ray, the ultrasonic scan and the customer's return form one at a time, it turns out the cause isn't in the chip itself (see What does the customer liaison at a test-and-assembly house do?).

The companies, chips, people, lot numbers and figures in the game are fictional; how failure analysis is done, and why the harmless steps come before the destructive ones, come from public, general sources. For other jargon, see Chip fab jargon in plain English.