What is WAT, and how does a wafer map show what went wrong?

In a chip fab, WAT stands for wafer acceptance test, also called PCM or parametric test. When the wafers are finished and before they leave the fab, probes touch small structures on the wafer that are there only for measuring, and read basic numbers such as transistor current, resistance and leakage to judge whether the lot was made right. A wafer map is a second report card: after wafer sort has tested every chip, each result is drawn in its place on the wafer. WAT answers "did the process drift?"; a wafer map answers "where are the bad chips, and what shape do they make?". A ring, one side, a line or a neat grid of bad chips often points to a different problem.

How wafer sort works is in How are chips tested?. This article is about reading the results.

What does WAT measure, and why not measure the chips?

On a wafer, the chips are separated by narrow gaps called scribe lines. When the wafer is cut apart (dicing), the blade runs along them. Since that area will be cut away anyway, engineers put small structures there just for measuring, called test keys.

Test keys are simple: one transistor on its own, a long resistor, a chain of contacts. Each is wired to a few metal pads that the probes can touch directly. They are made at the same time as the chips next to them and go through exactly the same steps.

Why not measure the chips themselves? A chip packs tens of millions to more than ten billion switches together, and working out the voltage at which one kind of transistor turns on from how the whole chip behaves is hard. It's like a building site: a few test samples are cast from the same truckload of concrete and crushed to see how strong they are. Nobody has to break a wall to know whether that load was good.

What numbers does WAT give?

The common ones:

• Transistors: the voltage at which they start to turn on (the threshold voltage), how much current flows when fully on, and how much leakage there is when off.
• Resistance: how well a layer conducts (sheet resistance), and the resistance of the contacts.
• A long chain of contacts: thousands joined in a row. If one is broken, the whole chain is open, so a single measurement shows whether any of them failed to connect.
• Insulating layers: their capacitance, and how much voltage they take before breaking down.

Only a few sites on each wafer are measured, spread across the middle and the edge, with the same few dozen tests at each site. A few points are much faster than testing every chip, so WAT is often one of the first places a whole lot shows up as off. Usually the lot moves on to wafer sort only when every number is within spec; if one item is out, the lot is put on hold until an engineer decides.

What does it mean when one WAT item fails?

It doesn't mean the chips are bad. It means some step may have drifted. Which item is off often points to the steps related to it: high contact resistance, for example, may mean the contact holes weren't etched all the way down or weren't completely filled.

But the first move is often to doubt the measurement before the process. If the needle tips on a probe card pick up dirt, the contact is poor and the resistance reads high, which looks just like a process problem. If the needles are cleaned, the wafer is probed again and the number comes back, it was never the process.

Test keys are spread across the whole wafer, so WAT numbers can also be laid out by position: how the center compares with the edge, and one wafer with the next. Each lot's numbers also go on control charts, and a slow drift to one side is a warning (see What is an SPC control chart?).

How is a wafer map different from WAT?

	WAT	Wafer map
Measures	Test keys in the scribe lines	Every one of the customer's chips
How many points	A few sites per wafer	Every chip
Answers	Did the process drift?	Which chips failed, and where?

After wafer sort, each chip goes into a bin, and the bins are drawn by position as the wafer map: one color for good, one for bad, sometimes another for off. Yield counts how many are good (see What does "yield" mean in chip news?); the wafer map tells you one thing more: where the bad ones are.

What do the common shapes on a wafer map point to?

A public data set often used in research holds more than 800,000 real wafer maps. About a fifth of them are labeled with one of nine kinds (one kind is "no pattern"), such as a cluster in the center, a ring at the edge, a scratch and random scatter. Below are the directions textbooks and papers often mention. Each one "often points to" something; none of them is an answer:

• Scattered with no pattern: looks more like randomly falling particles. There is rarely a single cause; the fix is a cleaner cleanroom and cleaner tools (see How clean is a cleanroom?).
• Clustered in the center: some step treated the center differently from the outer area, for example uneven polishing, a stain left by chemicals, or a fault in part of a tool.
• A ring at the edge: the outermost band of a wafer is harder to make even than the middle, because gas, temperature and plasma behave differently there. Engineers often check steps that have to be even across the wafer first: thin film, etch, polishing, heating.
• One side, or one patch: that side may have been treated differently at some step.
• A line or an arc: often a scratch, for example from a robot arm, or a hard particle dragged across the wafer during polishing.
• A neat grid: one bad chip at a fixed spacing. If the spacing matches the field the scanner prints in one exposure, the problem often travels with the photomask: one speck on the mask prints again in every field (see What does a mask engineer do?). If the spacing matches the number of chips a probe card touches at once, suspect one set of needles on the probe card. That may be a measurement problem.
• Almost the whole wafer bad: a step may have gone badly wrong across the whole wafer, or the test itself may be the problem.

Real wafer maps often show two shapes on top of each other, and wafers from the same lot went through the same steps, so their maps often look alike.

Once you see a shape, what's next?

A shape only narrows things down. Common next steps:

1. Rule out the measurement: clean the needles, probe again, or check with a wafer whose answers are already known.
2. Compare wafer by wafer: is it on every wafer, or does it start from a certain one? A sudden start often means something changed at that point.
3. Check the records: list the tools the bad wafers went through and look for the one they all shared.
4. Cut it open: make a cross-section through a bad chip and look at it under an electron microscope (for example a TEM): a hole that wasn't filled, a broken line, or an extra layer?
5. Look at other numbers too: if the wafer map shows a ring at the edge, are the WAT numbers at the edge off as well? (For how steps are checked along the way, see How does a chip fab know each step went right?)

In fab24hr

In chapter 3 of the main story, The life of a chip, "The shape of a failure", you are the R&D line's R&D integration engineer (see What does an R&D integration engineer do?), a month or two after wafer start. The WAT for R-0912, the first lot of the hearing-aid chip "Glowmere", is back: wafer 9's contact resistance is 30% over spec. Hsiao-Wen in the Electrical test lab asks you: probe it again, or write it into the report as a process problem? If you gave Zhou a wafer for cross-sectioning in chapter 1, he tells you what he saw when he cut it open.

Then Hsiao-Wen puts three wafer maps on the screen: green is normal, red is failed, orange is fast. On each one you tap what's different: the ring at the edge of wafer 3 (not broken, just fast), the repeating grid from wafer 8 on, and the arc on wafer 11. At the 16:00 mask meeting, you also decide whether the next mask set leaves two spots inside the chip for your own test keys.

In A day in the fab, on the "Your role today" card, tap "R&D line" and swipe to the R&D integration engineer; the afternoon shift is the same day (shifts follow the time on your device). The company, chip, people, lot numbers and figures in the game are fictional; what WAT and wafer maps are and how to read them come from public, general sources. For other jargon, see Chip fab jargon in plain English.