Why do bigger chips have lower yield? Defect density, yield models and how yield improves

Bigger chips have lower yield because defects land on the wafer at random, like dust: one killer defect is enough to ruin a chip, and the bigger the chip, the more likely it is to be hit. The simplest model says yield is about e to the power of minus (chip area × defect density).

What yield is, and why multiplying hundreds of steps keeps it from ever reaching 100%, is covered with a cookie analogy in "What does "yield" mean in chip news?". This article goes one layer down.

What is defect density?

Things too small to see always land on a wafer: particles and residue (see "What is wafer defect inspection?"). If one lands somewhere that doesn't matter, the chip still works. Only the ones that break a line, or join two lines that should stay apart, are "killer" defects.

Defect density is the average number of killer defects per unit of area, usually counted per square centimeter and often written D0. It tells you how clean and how steady a production line is.

Why are bigger chips hit more often?

Picture 100 killer defects falling at random on one wafer. Cut it into 1,000 small chips, and each chip gets 0.1 defects on average; cut it into 100 big chips, and each gets 1 on average.

An average of 1 doesn't mean every chip is hit: some get two or three, some get none, and only the ones with none are good. The simplest way to work out that chance, found in textbooks, is the Poisson model:

Yield ≈ e to the power of minus (chip area × defect density), written Y ≈ e^(−A×D0)

e is a constant from math, about 2.718, and "area × defect density" is simply how many defects each chip gets on average. Plug in the numbers:

Chips per wafer	Average defects per chip	Share good	Good chips
1,000 (small chips)	0.1	90%	905
400	0.25	78%	312
200	0.5	61%	121
100 (big chips)	1	37%	37

(Illustrative numbers; the partial chips around the wafer's edge are left out.)

Make the chip 10 times bigger and the wafer holds 10 times fewer, but the good ones drop more than twentyfold (from 905 to 37). So each good big chip gets expensive fast (see "Why are chips so expensive?"). That's one reason a big chip is sometimes split into a few chiplets, each tested on its own and then packaged together: small pieces yield better (see "The news says "advanced packaging". What is it?").

Is the model accurate?

It's a starting point. Real fabs usually have to account for two more things:

• Defects often cluster: several pile onto the same few chips, and their neighbors escape, so big chips often yield a little better than the model says. Engineers use models with one more number for how tightly the defects cluster.
• Some failures aren't random: when a step drifts, a photomask has a spot of dirt or a wafer gets scratched in handling, the failures form a ring, a repeating grid or an arc, and they don't follow the random model above. These are called systematic problems, and they are counted separately.

What kinds of yield are there?

On the way from wafer start to shipping, yield is usually counted in three places (names and splits vary; this is one common way):

Yield	When	What it counts
Line yield (fab yield)	When the fab finishes	The share of wafers started that weren't scrapped along the way
Wafer sort yield (CP)	Before the wafer is cut	The share of chips on the wafer that pass wafer sort
Final test yield (FT)	After packaging	The share of packaged chips that pass final test

Multiply the three to get the share that finally ships: say 95%, 85% and 98%, which comes to about 79%. The yield article above is mostly about the second one. So when you see a yield figure, ask which one it is, and how big the chip is (for how the two tests work, see "How are chips tested?").

How does a new process climb, step by step?

When a new process or a new chip first goes through a pilot run, the yield is often low. Pulling it up stage by stage is called yield learning, and drawn as a graph, it's what the news calls a "yield ramp". One round goes roughly like this:

Step 1: Sort the failures and find the most common one

What: after wafer sort, failed chips go into different bins by how they failed, and the bins are ranked from most to fewest in a bar chart (a Pareto chart). Why: people and time are limited, and fixing the most common failure raises yield fastest. Otherwise: everything gets a little attention and nothing gets finished.

Step 2: See where the failures are, and narrow it down

What: draw the most common failure on a wafer map and compare it with the in-line defect inspection and the WAT results. Why: failures scattered with no pattern look like random particles; a ring or a repeating grid usually points to one step, one tool or a photomask (see "What is WAT, and how does a wafer map show what went wrong?"). Otherwise: you know "15% failed" but not which step to look at.

Step 3: Find the cause, fix it, and prove the fix works

What: check which tool the failed wafers all went through, and cross-section a chip if needed; then change a setting, repair the tool or replace the mask. Why: a shape is only a clue, and after a change you still need the next lot's numbers to come back. Otherwise: you may fix the wrong thing, or one lucky lot convinces you it's solved.

Step 4: Go back to step 1 for the next one

What: once the most common failure is fixed, the one that was second comes to the top, and another round starts. Why: each fix lifts the yield another stage. Early on, there are often a few big systematic problems; later, what's left is smaller and harder to find, and much of it is random defects, which come down mainly through a cleaner line that pushes defect density lower bit by bit, so the climb slows. Otherwise: the yield stalls halfway.

Which mistake shows up where?

The slowest part of each round is waiting for results: from wafer start to wafer sort takes weeks to months (see "How long does a wafer take to make?"). That's why in-line measurement and defect inspection matter so much: the sooner you see a problem, the sooner you can fix it. Here is an illustrative table (in reality, one mistake often leaves clues in several places):

What went wrong	Where it shows first	What shows later
Implant put in too few atoms	High sheet resistance on a monitor wafer	WAT: the voltage where the switch turns on is off
CMP polished too far	Thickness after polishing is too thin	Wires have higher resistance
Two layers misaligned	Overlay measurement after litho	Holes miss their target: higher resistance or an open
A contact not etched all the way down	Hard to see along the way	WAT: a long chain of contacts has high resistance or is open
A particle on the wafer	Defect inspection	Failed chips scattered across the wafer map with no pattern
A small flaw that hasn't failed yet	Passes every test	Fails after some use; burn-in can catch it first

If yield is poor, are the chips you buy more likely to fail?

A little more likely, but that isn't the main effect. Every chip is tested before it ships, and most of the bad ones are caught. So the most direct effect of poor yield is that each good chip costs more, and there may not be enough of them.

One thing to add, though: some defects aren't big enough to kill a chip right away. They leave a weak spot that passes every test and then fails after days or weeks of use; this is called an early-life failure. Studies have found that on wafers with poor yield, the chips that passed are also more likely to fail early, and the same goes for good chips in an area of the wafer where many chips failed. So products with strict requirements get an extra screen: burn-in (see "What is burn-in?"), or setting aside wafers whose yield is clearly worse than usual.

In fab24hr

In chapter 3 of the main story, The life of a chip, "The shape of a failure", you are the R&D line's R&D integration engineer. Wafer sort is done on R-0912, the first lot of the hearing-aid chip "Glowmere", and Hsiao-Wen in the Electrical test lab puts three wafer maps on the screen. On each one you tap the shape that's wrong: the ring at the edge of wafer 3 (fast, not failed), the repeating grid from wafer 8 on (it follows the photomask), and the arc on wafer 11 (scratched in handling). None of the three is random dust; each is a systematic problem with a cause you can find.

At the afternoon mask meeting, Hsin-Yi wants to keep two spots inside the chip for the R&D line's own test keys, and Manager Wang says: "Two spots is 2% more chip area. The customer will ask." The game doesn't work it out further; by this article's math, a little more area means a few fewer chips per wafer, and a slightly bigger target for defects.

In A day in the fab, on the "Your role today" card, tap "Production fab", swipe to the process engineer and tap "Etch" under the name: a yield improvement analysis sits on your desk, scheduled for today. Go back to your desk on the afternoon shift and open it: it was last saved three days ago, and today's progress is 4 minutes.

The company, chips, people, lot numbers and figures in the game are fictional; defect density, yield models and yield learning come from public, general sources, and the numbers in the tables are illustrative. For other jargon, see Chip fab jargon in plain English.